• 대한전자공학회논문지
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• 제25권5호
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• 한국음향학회지
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• 제8권5호
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• pp.95-101
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• 1989

일반 DSP들은 새로운 algorithm 및 응용 system의 개발을 위해서 전용 development system 및 simulator가 필수 불가결의 요소이다. 그러나 대부분 development system은 일반화된 내부 구조에 의해 그 유연성에 한계가 존재한다. 본 연구에서는 A/D입력과 D/A출력 data를 저장하는 buffer의 길이를 program에 의해 1 sample 단위부터 최대 2K sample 단위까지 가변할 수 있도록 하고, 이들 buffer도 2중 구조로 하여 연속 신호의 처리가 가능도록 한 DSP평가용 system을 개발하였다.

• 한국통신학회논문지
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• 제22권11호
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• pp.2521-2530
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• 1997

In this paepr, we present a video-on-demand (VOD) system design model that address and integrates a number of inter-related issues. Then with analysis and performance evaluation, we investigate various aspects of disk and buffer managements in the given model. Based on the analysis results, we suggest that a distributed buffering scheme with intermediate buffers may te useful to transform bursty disk accesses into a continuous stream for for glitch-free performance of VOD systems. Also, through simulation, we illustrate that massive multimedia information storage design techniques such as prefetching, clustered striping, and real-time disk scheduling integrated with the distributed buffering mechanism may enhance end-to-end real-time performance of VOD systems under wide-area networks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.109-112
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• 2002

This paper presents relationship between the dynamic behavior of an asynchronous linear pipeline (ALP) and the performance of the ALP as buffers are allocated. Then the relationship is used in order to characterize a local optimum situation on the buffer design space of the ALP. Using the characterization we propose an efficient algorithm optimizing buffer allocation on an ALP in order to achieve its average case performance. Without the loss of optimality, our algorithm works in linear time complexity so it achieves fast buffer-configuration optimization. This paper makes two contributions. First, it describes relationship between the performance characteristics of an ALP and a local optimum on the buffer design space of the ALP. Second, it devises a buffer allocation algorithm finding an optimum solution in linear time complexity.

• 대한산업공학회지
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• 제22권3호
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• pp.313-324
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• 1996

A new policy to determine the waiting position of an idle Automated Guided Vehicle(AGV) is proposed and its performance is compared with the existing waiting position policies. Unlike the existing policies, the queue length in the input buffer is considered in the new policy. As a result, the waiting position based on the new policy depends on the status of the system. The simulation result indicates that the proposed policy reduces the waiting time in both the input and the output buffers significantly, regardless of the number of AGVs in the system. Therefore, the manufacturing lead time can be minimized.

• 산업기술연구
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• 제27권B호
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• pp.215-219
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• 2007

For Web server implementations, there are 4 main schemes: process-per-request (PPR), thread-per-request (TPR), worker thread pool (WTP), and worker thread pool with buffers (WTPB). This paper compares performance of the schemes in response time point of view. WTPB shows the best performance. The appropriate number of worker threads for WTPB depends on the request service time. For short requests, the number can be very small. But for longer requests, it is about 1/6 of the number of simultaneous connections.

• 한국군사과학기술학회지
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• 제5권2호
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 가을 학술발표논문집 Vol.30 No.2 (1)
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• pp.304-306
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• 2003

실시간 운영 체제(Real-Time Operating Systems)는 시스템 동작이 논리적 정확성뿐만 아니라 시간적 정확성에도 좌우되는 운영 체제이다. 그리고 실시간 운영체제는 멀티태스킹(Multitasking) 과 ITC(Inter Task Communication)을 제공한다는 점에서 일반 운영 체제인 Windows, Linux, Unix등과 같지만 시간 결정성을 보장해야 한다는 점에서 일반 운영 체제와 다르다. 이러한 실시간 운영체제에서 프로그래머가 디버그 정보를 알기 위해서 여러 가지 기법을 사용하게 된다. 본 논문은 실시간 운영체제에서 시간 결정성을 지키면서 메모리에 관련된 디버그 이벤트들을 알기 위한 버퍼의 설계 및 구현에 대해 기술한다.

• Journal of Pharmaceutical Investigation
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• 제30권4호
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• pp.295-297
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• 2000

A new method to evaluate erosion of biodegradable polymer, polyanhydrides, was developed. The polymer devices were prepared with the melt-casting method and weight loss was accurately measured after agitating the devices in buffers (pH 1-9), and removing the device at selected time intervals and freeze-drying the device. The erosion rate was estimated from the plot of the weight loss(%) of device as a function of time. The freeze-drying technique used in this study is particularly useful for estimating the erosion rate of biodegradable polymer.

• 대한전자공학회논문지
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• 제24권2호
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.