• Title/Summary/Keyword: Time Buffers

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Approximate analysis of the serial production lines (분할기법을 이용한 직렬 생산라인의 근사화 해석)

  • 서기성;강재현;이창훈;우광방
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.406-410
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    • 1990
  • This paper presents an approximate analysis of the serial production lines using decomposition technique. A serial production line consists of a series of unreliable machines separated by finite buffers. The serial production line is evaluated by approximation method, the results of which are compared with those examined by the discrete time event simulation, based on this approximation method, a gradient technique is proposed, which improves the efficiency of an operation of production line through the re-allocation of buffers.

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Analysis of Optimal Buffer Capacities in 3-node Tandem Queues with Blocking (3-노(盧)드 유한 버퍼 일렬대기행렬에서의 최적 버퍼 크기에 대한 분석)

  • Seo, Dong-Won
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2005.05a
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    • pp.881-889
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    • 2005
  • In this study, we consider characteristics of waiting times in single-server 3-node tandem queues with a Poisson arrival process, finite buffers and deterministic or non-overlapping service times at each queue. There are three buffers: one at the first node is infinite and the others are finite. The explicit expressions of waiting times in all areas of the systems, which are driven as functions of finite buffer capacities, show that the sojourn time does not depend on the finite buffer capacities and also allow one to compute and compare characteristics of waiting times at all areas of the system under two blocking policies: communication and manufacturing blocking. As an application of these results, moreover, an optimization problem which determines the smallest buffer capacities satisfying predetermined probabilistic constraints on waiting times is considered. Some numerical examples are also provided.

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Performance analysis of the IeEE 802.4 token passing system with finite buffers (유한한 버퍼를 가지는 IEEE 802.4 토큰패싱시스템의 성능해석)

  • 박정우;문상용;권욱현
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.7
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    • pp.11-20
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    • 1996
  • In this paper, the performance of the IeEE 802.4 token-passing is analyzed under the assumption that all nodes have finite buffers and finite THT (token tolding time). The loads generated at nodes are assumed to be asymmetric. The priority mechanism is not considered. This paper derives an approximate matrix equation of the queue length distributin in terms of the number of nodes, frame arrival rate and mean service time of a frame in steady state. Based on the matrix equation, the mean token rotation time, the mean waiting time and the blocking probability are derived analytically. the analytic results are compared with simulation results in order to show that the deviations are small.

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Symbol Timing Alignment and Combining Technique in Rake Receiver for cdma2000 Systems (cdma2000 시스템용 레이크 수신기에서의 심볼 정렬 및 컴바이닝 기법)

  • Lee, Seong-Ju;Kim, Jae-Seok;Eo, Ik-Su;Kim, Gyeong-Su
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.1
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    • pp.34-41
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    • 2002
  • In the conventional rake receiver structure for the IS-95 CDMA system, each finger has its own time-deskew buffer or FIFO that aligns the multipath signals to the same timing reference in order to combine symbols. This architecture is not a burden to the rake receiver design mainly because of the small number and size of the buffers. However, the number and size of the buffers are significantly increased in the cdma2000 system which adopts multiple carriers and the small spreading gain for a higher rate in data services. In order to decrease the number of buffers, we propose a new model of the time-deskew buffers, which combines the symbols as well as realigns them at the same time. Our architecture reduces the hardware complexity of the buffers by about more than 60% and 70% compared with the conventional one when we consider each rake receiver has three and four independent fingers, respectively. Moreover, the proposed algorithm is very useful not only to the cdma2000 rake receiver but also to the receiver with many fingers in order to increase the BER performance.

Performance Analysis of Time Division Multiplexed Optical Output Buffers (시간 분할 다중합 광 출력 버퍼의 성능 분석)

  • 정준영;고광철;정제명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.9B
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    • pp.751-759
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    • 2003
  • We analyze the performances, such as the cell loss probability(CLR) and the cell delay time, of time division multiplexed(TDM) optical output buffers using traveling delay lines or delay-line loops for buffering. Since traveling delay lines used for buffering are superior over delay-line loops in terms of simplicity and signal quality, they were used in a conventional TDM optical output buffer. However, the latter is more flexible than the former in that the cell storage time is adjustable by changing the recirculating times of a cell in the loops. So we propose a novel TDM optical output buffer using delay-line loops for buffering. We show that the proposed TDM optical output buffer can reduce the number of buffering unit required to achieve a CLR of less than 10$^{-9}$ . When the number of buffering unit is sufficiently large, we show that both TDM optical output buffers have same cell delay time characteristic.

FPGA Implementation for Real Time Sobel Edge Detector Block Using 3-Line Buffers (3-Line 버퍼를 사용한 실시간 Sobel 윤곽선 추출 블록 FPGA 구현)

  • Park, Chan-Su;Kim, Hi-Seok
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.10-17
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    • 2015
  • In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

Minimizing the Total Stretch in Flow Shop Scheduling with Limited Capacity Buffers (한정된 크기의 버퍼가 있는 흐름 공정 일정계획의 스트레치 최소화)

  • Yoon, Suk-Hun
    • Journal of Korean Institute of Industrial Engineers
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    • v.40 no.6
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    • pp.642-647
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    • 2014
  • In this paper, a hybrid genetic algorithm (HGA) approach is proposed for an n-job, m-machine flow shop scheduling problem with limited capacity buffers with blocking in which the objective is to minimize the total stretch. The stretch of a job is the ratio of the amount of time the job spent before its completion to its processing time. HGA adopts the idea of seed selection and development in order to improve the exploitation and exploration power of genetic algorithms (GAs). Extensive computational experiments have been conducted to compare the performance of HGA with that of GA.

An Adaptive Buffering Method for Practical HTTP Live Streaming on Smart OTT STBs

  • Kim, Hyun-Sik;Kim, Inki;Han, Kyungsik;Kim, Donghyun;Seo, Jong-Soo;Kang, Mingoo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.3
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    • pp.1416-1428
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    • 2016
  • In this paper, we address the channel zapping time problem of video streaming services based on HTTP Live Streaming (HLS) on smart Over-The-Top Set-Top Boxes (OTT STBs). Experimental analysis of the channel zapping time, show that smart OTT STBs inevitably suffer from the accumulated zapping time through channel change request, Internet Group Management Protocol (IGMP) leave/join, synchronization delay, video buffer delay, and STB processing delay when providing HLS services. As a practical solution for the zapping time reduction, an adaptive buffering method is proposed. The proposed method exploits two adaptive buffers added to the basic HLS player. These two adaptive buffers are responsible for constantly buffering previous and next channels relative to the current channel. Implementation and test results show that a stable zapping time less than one second can be achieved even under diverse video bitrate changes and varying network conditions by the proposed adaptive buffering method.

Petri Net Modeling and Analysis for Periodic Job Shops with Blocking

  • Lee, Tae-Eog;Song, Ju-Seog
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1996.04a
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    • pp.314-314
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    • 1996
  • We investigate the scheduling problem for periodic job shops with blocking. We develop Petri net models for periodic job shops with finite buffers. A buffer control method would allow the jobs to enter the input buffer of the next machine in the order for which they are completed. We discuss difficulties in using such a random order buffer control method and random access buffers. We thus propose an alternative buffer control policy that restricts the jobs to enter the input buffer of the next machine in a predetermined order. The buffer control method simplifies job flows and control systems. Further, it requires only a cost-effective simple sequential buffer. We show that the periodic scheduling model with finite buffers using the buffer control policy can be transformed into an equivalent periodic scheduling model with no buffer, which is modeled as a timed marked graph. We characterize the structural properties for deadlock detection. Finally, we develop a mixed integer programming model for the no buffer problem that finds a deadlock-free optimal sequence that minimizes the cycle time.

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Performance evaluation of the input and output buffered knockout switch

  • Suh, Jae-Joon;Jun, Chi-Hyuck;Kim, Young-Si
    • Korean Management Science Review
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    • v.10 no.1
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    • pp.139-156
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    • 1993
  • Various ATM switches have been proposed since Asynchronous Transfer Mode (ATM) was recognized as appropriate for implementing broadband integrated services digital network (BISDN). An ATM switching network may be evaluated on two sides : traffic performances (maximum throughput, delay, and packet loss probability, etc.) and structural features (complexity, i.e. the number of switch elements necessary to construct the same size switching network, maintenance, modularity, and fault tolerance, etc.). ATM switching networks proposed to date tend to show the contrary characteristics between structural features and traffic performance. The Knockout Switch, which is well known as one of ATM switches, shows a good traffic performance but it needs so many switch elements and buffers. In this paper, we propose an input and output buffered Knockout Switch for the purpose of reducing the number of switch elements and buffers of the existing Knockout Switch. We analyze the traffic performance and the structural features of the proposed switching architecture through a discrete time Markov chain and compare with those of the existing Knockout Switch. It was found that the proposed architecture could reduce more than 40 percent of switch elements and more than 30 percent of buffers under a given requirement of cell loss probability of the switch.

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