Reduction of Barrier Height between Ni-silicide and p+ source/drain for High Performance PMOSFET (고성능 PMOSFET을 위한 Ni-silicide와 p+ source/drain 사이의 barrier height 감소)
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- Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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- 2008.11a
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- pp.157-157
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- 2008