• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.295-299
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• 1999

The (S $r_{1-x}$C $a_{x}$)Ti $O_3$(SCT) thin films are deposited on Pt-coated electrode(Pt/TiN/ $SiO_2$/ Si) using RF sputtering method with substitutional contents of Ca. The maximum grain of thin films is obtained by substitution of Ca at 15[mol%]. The dielectric constant was increased with increasing the substitutional contents of Ca, while it was decreased if the substitutional contents of Ca exceeded over 15[mo1%]. The dielectric constant changes almost linearly in temperature ranges of -80~ +90[$^{\circ}C$]. The temperature properties of the dielectric loss have a stable value within 0.02 independent of the substitutional contents of Ca. All SCT thin films used in this study show the phenomena of dielectric relaxation with the increase of frequency, and the relaxation frequency is observed above 200(kHz).)..

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.196-196
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• 2008

We have investigated that the effect of post annealing on the structural and electrical properties of $Ba_{0.5}Sr_{0.5}TiO_3$ thin films. The BST thin films were deposited on n-type 4H-silicon carbide(SiC) using pulsed laser deposition (PLD). The deposition was carried out in oxygen ambient 100mTorr for 5 minutes, which results in about 300nm-thick BST films. For the BST/4H-SiC, 200nm thick silver was deposited on the BST films bye-beam evaporation. The X-ray diffraction patterns of the BST films revealed that the crystalline structure of BST thin films has been improved after post-annealing at $850^{\circ}C$ for 1 hour. The root mean square (RMS) surface roughness of the BST film measured by using a AFM was increased after post-annealing from 5.69nm to 11.49nm. The electrical properties of BST thin film were investigated by measuring the capacitance-voltage characteristics of a silver/BST/4H-SiC structure. After the post-annealing, dielectric constant of the film was increased from 159.67 to 355.33, which can be ascribed to the enhancement of the crystallinity of BST thin films.

• Current Photovoltaic Research
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• v.7 no.1
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• pp.9-14
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• 2019

Carrier selective solar cell structure has allured curiosity of photovoltaic researchers due to the use of wide band gap transition metal oxide (TMO). Distinctive p/n-type character, broad range of work functions (2 to 7 eV) and risk free fabrication of TMO has evolved new concept of heterojunction intrinsic thin layer (HIT) solar cell employing carrier selective layers such as $MoO_x$, $WO_x$, $V_2O_5$ and $TiO_2$ replacing the doped a-Si layers on either front side or back side. The p/n-doped hydrogenated amorphous silicon (a-Si:H) layers are deposited by Plasma-Enhanced Chemical Vapor Deposition (PECVD), which includes the flammable and toxic boron/phosphorous gas precursors. Due to this, carrier selective TMO is gaining popularity as analternative risk-free material in place of conventional a-Si:H. In this work hole selective materials such as $MoO_x$, $WO_x$ and $V_2O_5$has been investigated. Recently $MoO_x$, $WO_x$ & $V_2O_5$ hetero-structures showed conversion efficiency of 22.5%, 12.6% & 15.7% respectively at temperature below $200^{\circ}C$. In this work a concise review on few important aspects of the hole selective material solar cell such as historical developments, device structure, fabrication, factors effecting cell performance and dependency on temperature has been reported.

• Proceedings of the KAIS Fall Conference
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• 2000.10a
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• pp.42-42
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• 2000

반응소결 탄화규소는 소결체 내에 잔존 실리콘이 남아 있어 고온강도의 감소를 초래하는 단점이 있어 고온 구조재료로서의 사용이 제한되어 왔다. 따라서 이러한 문제점을 해결하기 위한 방법으로 Si 단독으로 용응침투시키는 대신 Si-MoSi₂를 침투시키는 방법이 시도되고 있으며, 이외에도 TiC 성형체에 Co, Ni 등의 금속, ZrB₂ 성형체에 Zr 금속 등을 용융, 침투시켜 성능향상을 유도하는 연구가 진행되고 있다. 본 연구에서는 반응소결에 대한 기본이론과 응용분야, 반응소결 비산화물계 세라믹스의 제조공정 및 이들 소결체의 미세구조와 기계적 특성 등을 소개하고자 한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.193-198
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• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of Photoscience
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• v.12 no.1
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• pp.17-23
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• 2005

Application of a new photocatalyst has been attempted to improve the efficiency and rates of photocatalytic degradation of azo dyes by using a model dye such as Methyl Orange. As a new photocatalyst, $TiO_2$ encapsulated EFAL-removed zeolite Y ($TiO_2$ /EFAL-removed zeolite Y) has been synthesized by ion-exchange in the mixture of EFAL-removed zeolite Y with 0.05 M aqueous [$(NH_4)_2 TiO(C_2O_4)_2.H_2O$] [$TiO(C_2O_4)_2.H_2O$]. This new photocatalyst has been characterized by measuring XRD, IR and reflectance absorption spectra as well as ICP analysis, and it was found that the framework structure of $TiO_2$ /EFAL-removed zeolite Y is not changed by removing the extra-framework aluminum (EFAL) from the normal zeolite Y and the $TiO_2$ inside the photocatalyst exists in the form of $(TiO^{2+})_n$ nanoclusters. Based on the ICP analysis, the Si/Al ratio of the $TiO_2$ /EFAL-removed zeolite Y and the weight of $TiO_2$ were determined to be 23 and 0.061g in 1.0g photocatalyst, respectively. It was also found that adsorption of the azo dye in the $TiO_2$ /EFAL-removed zeolite is very effective (about 80 % of the substrate used). This efficient adsorption contributes to the synergistic photocatalytic activities of the $TiO_2$ /EFAL-removed zeolite by minimizing the required flux diffusion of the substrate. Thus, the photocatalytic reduction of methyl orange (MO) was found to be 8 times more effective in the presence of $TiO_2$ /EFAL-removed zeolite Y than in the presence of $TiO_2$ /normal zeolite Y. Furthermore, the photocatalytic reduction of MO by using 1.0 g of the $TiO_2$ /EFAL-removed zeolite Y containing 0.061g of $TiO_2$ is much faster than that carried out by using 1.0 g of Degussa P-25.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.19-23
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• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.77-81
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• 2020

Commercialization of flexible OLED displays, such as rollable and foldable displays, has attracted tremendous interest in next-generation display markets. However, during bending deformation, cracking and delamination of thin films in the flexible display panels are the critical bottleneck for the commercialization. Therefore, measuring mechanical properties of the fragile thin films in the flexible display panels is essential to prevent mechanical failures of the devices. In this study, tensile properties of the metal and ceramic nano-thin films were quantitatively measured by using a direct tensile testing method on the water surface. Elastic modulus, tensile strength, and elongation of the sputtered Mo, MoTi thin films, and PECVD deposited SiN_x thin films were successfully measured. As a result, the tensile properties were varied depending on the deposition conditions and the film thickness. The measured tensile property values can be applied to stress analysis modeling for mechanically robust flexible displays.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.211-212
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• 2010

GaN 기반의 상부발광형 LED는 동작되는 동안 생기는 전기적 단락, 그리고 칩 위의 p-형 전극과 n-형 전극 사이에 생기는 누설전류 및 신뢰성 확보를 위하여 칩 표면에 passivation 층을 형성하게 된다. SiO2, Si3N4와 같은 passivation layers는 일반적으로 PECVD (Plasma Enhanced Chemical Vapor Deposition)공정을 이용한다, 하지만 이는 공정 특성상 plasma로 인한 damage가 유발되기 때문에 표면 누설 전류가 증가 한다. 이로 인해 forward voltage와 reverse leakage current의 특성이 저하된다. 본 실험에서는 원자층 단위의 박막 증착으로 인해 PECVD보다 단차 피복성이 매우 우수한 PEALD(Plasma Enhanced Atomic Layer Deposition)공정을 이용하여 Al2O3 passivation layer를 증착한 후, 표면 누설전류와 빛의 출력 특성에 대해서 조사해 보았다. PSS (patterned sapphire substrate) 위에 성장된 LED 에피구조를 사용하였고, TCP(Trancformer Copled Plasma)장비를 사용하여 에칭 공정을 진행하였다. 이때 투명전극을 증착하기 위해 e-beam evaporator를 사용하여 Ni/Au를 각각 $50\;{\AA}$씩 증착한 후 오믹 특성을 향상시키기 위하여 $500^{\circ}C$에서 열처리를 해주었다. 그리고 Ti/Au($300/4000{\AA}$) 메탈을 사용하여 p-전극과 n-전극을 형성하였다. Passivation을 하지 않은 경우에는 reverse leakage current가 -5V 에서 $-1.9{\times}10-8$ A 로 측정되었고, SiO2와 Si3N4을 passivation으로 이용한 경우에는 각각 $8.7{\times}10-9$과 $-2.2{\times}10-9$로 측정되었다. Fig. 1 에서 보면 알 수 있듯이 5 nm의 Al2O3 film을 passivation layer로 이용할 경우 passivation을 하지 않은 경우를 제외한 다른 passivation 경우보다 reverse leakage current가 약 2 order ($-3.46{\times}10-11$ A) 정도 낮게 측정되었다. 그 이유는 CVD 공정보다 짧은 ALD의 공정시간과 더 낮은 RF Power로 인해 plasma damage를 덜 입게 되어 나타난 것으로 생각된다. Fig. 2 에서는 Al2O3로 passivation을 한 소자의 forward voltage가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 0.07 V와 0.25 V씩 낮아지는 것을 확인할 수 있었다. 또한 Fig. 3 에서는 Al2O3로 passivation을 한 소자의 output power가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 2.7%와 24.6%씩 증가한 것을 볼 수 있다. Output power가 증가된 원인으로는 향상된 forward voltage 및 reverse에서의 leakage 특성과 공기보다 높은 Al2O3의 굴절률이 광출력 효율을 증가시켰기 때문인 것으로 판단된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.