• Computers and Concrete
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• 제16권2호
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• pp.261-274
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• 2015

This study established the standard recommended values and expansion fracture threshold values for the content of steel slag in controlled low-strength materials (CLSM) to ensure the appropriate use of steel slag aggregates and the prevention of abnormal expansion. The steel slags used in this study included basic oxygen furnace (BOF) slag and desulfurization slag (DS), which replaced 5-50% of natural river sand by weight in cement mixtures. The steel slag mortars were tested by high-temperature ($100^{\circ}C$) curing for 96 h and autoclave expansion. The results showed that the effects of the steel slag content varied based on the free lime (f-CaO) content. No more than 30% of the natural river sand should be replaced with steel slag to avoid fracture failure. The expansion fracture threshold value was 0.10%, above which there was a risk of potential failure. Based on the scanning electron microscopy (SEM) analysis, the high-temperature catalysis resulted in the immediate extrusion of peripheral hydration products from the calcium hydroxide crystals, leading to a local stress concentration and, eventually, deformation and cracking.

• 동력기계공학회지
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• 제4권1호
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• pp.81-87
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• 2000

In this study, CT specimens were prepared from ASTM SA516 Gr. 70 which was used for pressure vessel plates for room and low temperature service. And we got the following characteristics from fatigue crack growth test carried out in the environment of room and low temperature at $25^{\circ}C,\;-60^{\circ}C,\;-80^{\circ}C\;and\;-100^{\circ}C$ and in the range of stress ratio of 0.05 by means of opening mode displacement. At the constant stress ratio, the threshold stress intensity factor range ${\Delta}K_{th}$ in the early stage of fatigue crack growth (Region I) and stress intensity factor range ${\Delta}K$ in the stable of fatigue crack growth (Region II) was increased in proportion to descend temperature. It assumed that the fatigue resistance characteristics and fracture strength at low temperature is considerable higher than that of room temperature in the early stage and stable of fatigue crack growth region. The straight line slope relation of logarithm $d{\alpha}/dN\;-{\Delta}K$ in Region II, that is, the fatigue crack growth exponent m increased with descending temperature at the constant stress ratio. It assumed that the fatigue crack growth rate $d{\alpha}/dN$ is rapid in proportion to descend temperature in Region II and the cryogenic-brittleness greatly affect a material with decreasing temperature.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2001년도 춘계학술발표대회 개요집
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• pp.224-227
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• 2001

In this study, CT specimens were prepared hem ASTM SA516 which was used for pressure vessel plates for room and low temperature service. And we got the following characteristics from fatigue crack growth test carried out in the environment of room and low temperature at $25^{\circ}C$, -3$0^{\circ}C$, -6$0^{\circ}C$, -8$0^{\circ}C$, -l$0^{\circ}C$ and -l2$0^{\circ}C$ and in the range of stress ratio of 0.1, 0.3 by means of opening mode displacement. At the constant stress ratio, the threshold stress intensity factor range $\Delta K_{th}$ in the early stage of fatigue crack growth ( Region I ) and stress intensity factor range $\Delta$K in the stable of fatigue crack growth ( Region II) was increased in proportion to descend temperature. It assumed that the fatigue resistance characteristics and fracture strength at low temperature is considerable higher than that of room temperature in the early stage and stable of fatigue crack growth region. The straight line slope relation of logarithm da/dN - $\Delta$K in Region II, that is, the fatigue crack growth exponent m increased with descending temperature at the constant stress ratio. It assumed that the fatigue crack growth rate da/dN is rapid in proportion to descend temperature in Region H and the cryogenic-brittleness greatly affect a material with decreasing temperature.

• 한국전자통신학회논문지
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• 제9권3호
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• pp.279-284
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• 2014

본 논문에서는 p-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 새로운 OLED 화소회로를 제안하였다. 제안한 5-TFT OLED 화소회로는 4개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. 제안한 화소회로의 한 프레임은 초기화 구간, 문턱전압 감지 및 데이터 기입 구간, 데이터 유지 구간 및 발광 구간으로 나누어진다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 ${\pm}0.25V$ 변동 시 최대 OLED 전류의 오차율은 -4.06%이였고 구동 트랜지스터의 문턱전압이 ${\pm}0.50V$ 변동 시 최대 OLED 전류의 오차율은 9.74%였다. 따라서 제안한 5T1C 화소회로는 p-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동에 둔감하여 균일한 OLED 전류를 공급함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.71-74
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• 1996

Ta$_2$O$_{5}$ film ale recognized as promising capacitor dielectric for future DRAM\`s. The electrical properties of Ta$_2$O$_{5}$films greatly depend on the heating condition. In the practical fabrication process, several annealing process, such as the annealing of Al in H$_2$(about 40$0^{\circ}C$) and reflow of BPSG (borophosphosilicate glass) film in $N_2$(about 80$0^{\circ}C$), exist after deposition of Ta$_2$O$_{5}$ film. In this paper, we describe the temperature effect on the electrical properties of W/Ta$_2$O$_{5}$/Si structure. The thin film of Ta$_2$O$_{5}$ and tungsten have been deposited on p-si(100) wafer using the sputtering system. The heating temperature was varied from 500 to 90$0^{\circ}C$ in $N_2$for 30min and The degree of temperature is 100\`C. In a log(J/E$^2$) Vs 1/E plot of typical I-V data, we find a linear relationship for the temperature of 500, $600^{\circ}C$ and as deposition. This could indicate Fowler-Nordheim tunneling as the dominant mode of current transports. However, we can not find a linear relationship for the temperature above $700^{\circ}C$. This could not indicate Fowler-Nordheim tunneling as the dominant mode of current transport. The high frequency (1MHz) capacitance-voltage (C-V) of W/Ta$_2$O$_{5}$/Si Capacitor were investigated on the basis of shift in the threshold voltage and dielectric constant. The magnitude of the threshold voltage and dielectric constant depends on the heating temperature, and increases with heating temperature.temperature.

• ETRI Journal
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• 제31권3호
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• pp.247-253
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• 2009

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

• 전자공학회논문지A
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• 제32A권6호
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• pp.75-81
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• 1995

InGaAsP/InP uncooled LDs emitting at 1.3$\mu$m wavelength are of interest for several application of fiber-to-the-home, optical interconnection, long-haul high-bit-rate optical transmission systems, etc. The strain compensated PBH-MQW-LD employing 1.4% compressive strained well (${\lambda}=1.3{\mu}m$) and 0.7% tensile strained barrier (${\lambda}=1.12{\mu}m$) layers grown by low pressure metallicorganic vapor phase epitaxy was found to be low threshold current and stable temperature characteristics. The average threshold current of 5.6mA and average slope efficiency of 0.27mW/mA at room temperature were obtained for uncoated uncooled-LD.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.170-172
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• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• 천문학논총
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• 제9권1호
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• pp.39-54
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• 1994

We present two codes which estimates virial mass and LTE mass using IMFORT interface within IRAF (Image Reduction and Analysis Facility). It is discussed that threshold value (temperature or CO integrated intensity), which defines a reasonable cloud boundary and size, is the most important parameter determining accurate results. Several virial masses are to be obtained using the vir task, as well as three velocity dispersions including the centroid velocity dispersion, a turbulence indicator. LTE mass is to be estimated by using task lte as well as three by-product images. The $^{13}CO$ abundance and threshold temperature of $^{13}CO$ and $^{12}CO$ peak temperatures are the most critical parameters in LTE technique.

• 대한전자공학회논문지
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• 제26권9호
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.