• 제목/요약/키워드: Three-dimensional Integration Circuits

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Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals

  • Gutmann, R.J.;Zeng, A.Y.;Devarajan, S.;Lu, J.Q.;Rose, K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권3호
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    • pp.196-203
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    • 2004
  • A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs

  • Jang, Cheoljon;Chong, Jong-Wha
    • ETRI Journal
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    • 제36권4호
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    • pp.635-642
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    • 2014
  • Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Quantitative Evaluation Method for Etch Sidewall Profile of Through-Silicon Vias (TSVs)

  • Son, Seung-Nam;Hong, Sang Jeen
    • ETRI Journal
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    • 제36권4호
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    • pp.617-624
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    • 2014
  • Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

저유전체 고분자 접착 물질을 이용한 웨이퍼 본딩을 포함하는 웨이퍼 레벨 3차원 집적회로 구현에 관한 연구 (A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive)

  • 권용재;석종원
    • Korean Chemical Engineering Research
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    • 제45권5호
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    • pp.466-472
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    • 2007
  • 웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.