• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1553-1555
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• 2008

Super-hydrophobic treated Polyimide film was used as a flexible substrate for developing a new method of metallization. Hydrophilic patterns were fabricated by IN irradiation through shadow mask. Patterned super-hydrophobic substrate was dipped into a bath containing silver nano ink Silver ink was only coated on hydrophilic patterned area. Metal lines of $600{\mu}m$ pitch were fabricated successfully. However, their thickness was too thin to serve as interconnection. To overcome this problem, iterative dipping was conducted. After repeating five times, the thickness of silver metal lines were increased to over than $2{\mu}$. After heat treatment of silver lines, their resistivities were reduced to order of $30{\mu}{\Omega}$-cm the similar level of values reported in other literatures. So, a new method of metallization has high potential for application of RFID antenna and flexible electronics substrates.

• 한국전기전자재료학회논문지
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• 제27권1호
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• pp.8-13
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• 2014

As packing density in integrated circuits increases, multilevel metallization process has been widely used. But hillock formed in the bottom layers of aluminum are well known to make interlayer short in multilevel metallization. In this study, the effects of ion implantation to the metal film and deposition temperature on the hillock formation were investigated. The Al-1%Si thin film of $1{\mu}m$ thickness was DC sputtered with substrate ($SiO_2/Si$) temperature of $20^{\circ}C$, $200^{\circ}C$, and $400^{\circ}C$, respectively. Ar ions ($1{\times}10^{15}cm^{-2}$: 150 keV) and B ions ($1{\times}10^{15}cm^{-2}$, 30 keV, 150 keV) were implanted to the Al-Si thin film. The deposited films were evaluated by SEM, surface profiler and resistance measuring system. As a results, Ar implanting to Al-Si film is very effective to reduce hillock size in the metal deposition temperature below than $200^{\circ}C$, and B implanting to an Al-Si film is effective to reduce hillock density in the high temperature deposition conditions around $400^{\circ}C$. Line width less than $3{\mu}m$ was free of hillock after alloying.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.938-940
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• 1999

We have fabricated SiC Schottky diode for high temperature applications. SiC thin film for drift region has been deposited by ICP-CVD. In order to establish metallization conditions, we have extracted the device parameters of the Schottky diode from the forward I-V characteristics and the C-V characteristics as a function of temperature. The ideality factor was varied from 2.07 to 1.15 and the barrier height was also varied from 1.26eV to 1.92eV with increase of temperature. The reverse blocking voltage was 183 V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1430-1432
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• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. To reduce these effects of the grain boundaries, we investigated various influencing factors such as preferential chemical etching of grain boundaries, grid design, transparent conductive thin film, and top metallization along grain boundaries. Pretreatment in $N_2$ atmosphere and gettering by $POCl_3$ and Al were performed to obtain polycrystalline silicon of the reduced defect density. Structural, electrical, and optical properties of solar cells were characterized. Improved conversion efficiencies of solar cell were obtained by a combination of Al diffusion into grain boundaries on rear side, fine grid finger, top Yb metal grid on Cr thin film of $200{\AA}$ and buried contact metallization along grain boundaries.

• Current Photovoltaic Research
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• 제2권4호
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• pp.173-176
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• 2014

We have investigated the seed layer formation of front side contact using the inkjet printing process. Conductive silver ink was printed on textured Si wafers with 80 nm thick $SiN_x$ anti reflection coating (ARC) layers and thickened by light induced plating (LIP). The inkjet printable sliver inks were specifically formulated for inkjet printing on these substrates. Also, a novel method to prepare nano-sized glass frits by the sol-gel process with particle sizes around 5 nm is presented. Furthermore, dispersion stability of the formulated ink was measured using a Turbiscan. By implementing these glass frits, it was found that a continuous and uniform seed layer with a line width of $40{\mu}m$ could be formed by a inkjet printing process. We also investigated the contact resistance between the front contact and emitter using the transfer length model (TLM). On an emitter with the sheet resistance of $60{\Omega}/sq$, a specific contact resistance (${\rho}_c$) below $10m{\Omega}{\cdot}cm^2$ could be achieved at a peak firing temperature around $700^{\circ}C$. In addition, the correlation between the contact resistance and interface microstructures were studied using scanning electron microscopy (SEM). We found that the added glass particles act as a very effective fire through agent, and Ag crystallites are formed along the interface glass layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1993년도 제5회 학술발표회 논문개요집
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• pp.80-81
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• 1993

• 전자공학회논문지A
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• 제31A권10호
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• pp.108-113
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• 1994

The characteristics of the oxidation prevention layers for the copper metallization were investigated. The thin films such as Cr, TiN and Al were used as the oxidation prevention layers for copper. Ultra thin aluminum films were found to prevent the oxidation of copper up to the highest oxidation annealing temperature among the barrier layers examined in this study. It was found that oxygen did not diffuse into copper through aluminum films because of the aluminum oxide layer formed on the aluminum surface and the ultra thin aluminum film could be a good oxidation barrier layer for the copper metallization.

• 한국재료학회지
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• 제16권4호
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• pp.257-263
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• 2006

We have investigated the effect of silver added to Cu films on the microstructure evolution, resistivity, surface morphology, stress relaxation temperature, and adhesion properties of Cu(Ag) alloy thin films deposited on Mo glue layer upon annealing. In addition, pure Cu films deposited on Mo has been annealed and compared. The results show that the silver in Cu(Ag) thin films control the grain growth through the coarsening of its precipitates upon annealing at $300^{\circ}C{\sim}600^{\circ}C$ and the grain growth of Cu reveals the activation energy of 0.22 eV, approximately one third of activation energy for diffusion of Ag dopant along the grain boundaries in Cu matrix (0.75 eV). This indicates that the grain growth can be controlled by Ag diffusion along the grain boundaries. In addition, the grain growth can be a major contributor to the decreased resistivity of Cu(Ag) alloy thin films at the temperature of $300^{\circ}C{\sim}500^{\circ}C$, and decreases the resistivity of Cu(Ag) thin films to $1.96{\mu}{\Omega}-cm$ after annealing at $600^{\circ}C$. Furthermore, the addition of Ag increases the stress relaxation temperature of Cu(Ag) thin films, and thus leading to the enhanced resistance to the void formation, which starts at $300^{\circ}C$ in the pure Cu thin films. Moreover, Cu(Ag) thin films shows the increased adhesion properties, possibly resulting from the Ag segregating to the interface. Consequently, the Cu(Ag) thin films can be used as a metallization of advanced TFT-LCDs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.