• Korean Journal of Materials Research
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• v.22 no.10
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Applied Chemistry for Engineering
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• v.24 no.4
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• pp.438-442
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• 2013

In the present work, electroless plating was used for coating thin films consisting mainly of Ni and P on carbon fiber. Structural changes appeared upon the post-annealing at various temperatures of the Ni-P film on carbon fiber was studied using various analysis methods. Scanning, a flat surface structure of Ni-P film on carbon fiber was found after electroless plating of Ni-P film on carbon fiber without post-annealing, whereas annealing at $350^{\circ}C$ resulted the formation of porous structures. With increasing the annealing temperature to $650^{\circ}C$ with an interval of $50^{\circ}C$, the pore size increased, but the density decreased. X-ray diffraction (XRD) showed the existence of metallic Ni, and Ni-P compounds before post-annealing, whereas the post-annealing resulted in the appearance of NiO peaks, and the decrease in the intensity of the peak of metallic Ni. Using X-ray photoelectron spectroscopy (XPS), phosphorous oxides were detected on the surface upon annealing at $650^{\circ}C$, and $700^{\circ}C$, which can be attributed to the phosphorous compounds originally existing in the deeper layers of the Ni films, which undergo sublimation and escape from the film upon annealing. Escape of phosphorous species from the bulk of Ni-P film upon annealing could leave a porous structure in the Ni films. Porous materials can be of potential applications in diverse fields due to their interesting physical properties such as high surface area, and methods for fabricating porous Ni films introduced here could be easily applied to a large-scale production, and therefore applicable in diverse fields such as environmental filters.

• Journal of the Korean Magnetics Society
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• v.15 no.2
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• pp.67-75
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• 2005

For th aim of lightweight microwave absorbers, conductive and magnetic microspheres are fabricated by plating of Co films on hollow ceramic microspheres of low density. Metal plating was carried out in a two-step electroless plating process (pre-treatment of activation and plating). Uniform coating of the film with about $2{\~}3{\cal}um$ thickness was identified by SEM. High-frequency magnetic and microwave absorbing properties were determined in the rubber composites containing the Co-coated microspheres. Due to conductive and ferromagnetic behavior of the Co thin films, high dielectric constant and magnetic loss can be obtained in the microwave frequencies. Due to those electromagnetic properties, high absorption rate (25 dB) and thin matching thickness ($2.0{\~}2.5{\cal}mm$) are predicted in the composite layers containing the metal-coated microspheres of low density (about 0.84 g/cc) for the electromagnetic radiation in microwave frequencies.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.23 no.2
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• pp.108-113
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• 2013

Chalcopyrite material $CuInSe_2$ (CIS) is known to be a very prominent absorber layer for high efficiency thin film solar cells. Current interest in the photovoltaic industry is to identify and develop more suitable materials and processes for the fabrication of efficient and cost-effective solar cells. Various processes have been being tried for making a low cost CIS absorber layer, this study obtained the CIS nanoparticles using commercial powder of 6 mm pieces for low cost CIS absorber layer by high frequency ball milling and cryogenic milling. And the CIS absorber layer was prepared by paste coating using milled-CIS nanoparticles in glove box under inert atmosphere. The chalcopyrite $CuInSe_2$ thin films were successfully made after selenization at the substrate temperature of $550^{\circ}C$ in 30 min, CIS solar cell of Al/ZnO/CdS/CIS/Mo structure prepared under various deposition process such as evaporation, sputtering and chemical vapor deposition respectively. Finally, we achieved CIS nanoparticles solar cell of electric efficient 1.74 % of Voc 29 mV, Jsc 35 $mA/cm^2$ FF 17.2 %. The CIS nanoparticles-based absorber layers were characterized by using EDS, XRD and HRSEM.

• Journal of the Korean Applied Science and Technology
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• v.24 no.2
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• pp.174-181
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• 2007

In this study, $SiO_2/poly(ethylene-co-vinyl$ alcohol)(EVOH) hybrid coating materials with gas barrier property could be produced using sol-gel method. The biaxially oriented polypropylene (BOPP) substrate with surface pretreatment was coated with the prepared hybrid sols containing various inorganic silicate component by a spin coating method. Crystallization behavior of the hybrids was investigated in terms of analysis of X-ray diffraction and cooling thermogram from DSC experiment. From the morphological observation of the $SiO_2/EVOH$ hybrid gel, it was confirmed that there existed an optimum content of inorganic silicate precursor, Tetraethylorthosilicate (TEOS), to produce hybrid materials with dense microstructure, exhibiting uniformly dispersed silica particles with average size below 100 nm. When TEOS was added at below or above the optimum content, particle clusters with large domain were observed, resulting in phase separation. This morphological result was found to be in good agreement with that of oxygen permeability of the hybrid coated films. In the case of film coated with hybrid prepared from addition of 0.01 - 0.02mol of TEOS, a remarkable improvement in barrier property could be obtained, however, with the addition of TEOS more than 0.04 mol, the barrier property was dramatically reduced because of phase separation and micro-crack formation on the film surface.

• The Journal of Korean Academy of Prosthodontics
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• v.41 no.2
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• pp.128-135
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• 2003

Statement of problem : Implant screw loosening remains a problem in implant prosthodontics. Some abutment screws with treated surfaces were introduced to prevent screw loosening and to increase preload. DLC(Diamond Like Carbon) film has similar properties on hardness, wear resistance, chemical stability, biocompatibility as real diamond materials. Purpose : The purpose of this study was to investigate the effect of lubricant layer on abutment screw and to discriminate more effective method between soft lubricant and hard lubricant to prevent screw loosening. Material and method : In this study, $1{\mu}m$ thickness DLC was used as protective, lubricating layer of titanium screws and 3 times removal torque was measured on the abutment screws to investigate the difference in 10 coated and 10 non-coated abutment screws. Results : The results indicated that the implants with DLC coating group were not more resistant to the applied force in screw loosening. At 32Ncm, the 3 times removal torque in DLC group were $27.75{\pm}2.89,\;25.85{\pm}2.35$ and $26.2{\pm}2.57$. The removal torque in no-coated abutment screws were $27.85{\pm}4.23,\;27.35{\pm}2.81$ and $27.9{\pm}2.31$, respectively. Conclusion : The lubricant layer used in this study was Diamond Like Carbon(DLC) and it have a properties of hard and stable layer. The DLC coating layer was hard enough to prevent distortion of screws in the repeated unscrewing procedure in clinical situation. The reduced friction coefficient in hard DLC layer was not effective to prevent screw loosening.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.195-198
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• 2008

In this paper, it was demonstrated that organic thin-film transistors (OTFTs) were fabricated with the organic passivation layer by vapor deposition polymerization (VDP) processing. In order to form polymeric film as a passivation layer, VDP process was also introduced instead of spin-coating process, where polymeric film was co-deposited by high-vacuum thermal evaporation from 6FDA and ODA followed by curing. In order to investigate by compared with different passivation layer, the other OTFTs is fabricated to passivation by Polyvinylalcohol using spincoating. We can see that two different ways of passivation layer affect electric characteristic of OTFTs. The initial electric characteristic of OTFTs before passivation such as field effect mobility, threshold voltage, and on-off current ratio are $0.24cm^2/Vs$, -3V, and $10^6$, respectively. Then after polyimide passivation layer, field effect mobility change from $0.24cm^2/Vs$ to $0.26cm^2/Vs$, threshold voltage from -3V to 1V and on-off current ratio from $10^6$ to $10^6$, respectively. In the case of polyvinylalcohol passivation, the initial electric characteristic of OTFTs before passivation such as field effect mobility, threshold voltage, and on-off current ratio are $0.13cm^2/Vs$, 0V, and $10^6$, respectively. Then after polyvinylalcohol passivation layer, field effect mobility changes from $0.13cm^2/Vs$ to $0.13cm^2/Vs$, threshold voltage from 0V to 2V, and on-off current ratio from $10^6$ to $10^5$, respectively.

• Progress in Superconductivity
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• v.12 no.2
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• pp.118-123
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• 2011

The properties of $2^{nd}$ generation high temperature superconducting wire, coated conductor strongly depend on the quality of superconducting oxide layer and property of metal substrate is one of the most important factors affecting the quality of coated conductor. Good mechanical and chemical stability at high temperature are required to maintain the initial integrity during the various process steps required to deposit several layers consisting coated conductor. And substrate need to be nonmagnetic to reduce magnetization loss for ac application. Hastelloy and stainless steel are the most suitable alloys for metal substrate. One of the obstacles in using stainless steel as substrate for coated conductor is its difficulties in making smooth surface inevitable for depositing good IBAD layer. Conventional method involves several steps such as electro polishing, deposition of $Al_2O_3$ and $Y_2O_3$ before IBAD process. Chemical solution deposition method can simplify those steps into one step process having uniformity in large area. In this research, we tried to improve the surface roughness of stainless steel(SUS310). The precursor coating solution was synthesized by using yttrium complex. The viscosity of coating solution and heat treatment condition were optimized for smooth surface. A smooth amorphous $Y_2O_3$ thin film suitable for IBAD process was coated on SUS310 tape. The surface roughness was improved from 40nm to 1.8 nm by 4 coatings. The IBAD-MgO layer deposited on prepared substrate showed good in plane alignment(${\Delta}{\phi}$) of $6.2^{\circ}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.421-427
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• 2009

We successfully fabricated 4.7-inch organic thin film transistors array with $640{\times}480$ pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing. The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 ^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 4.7-inch $640{\times}480$ OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than $150^{\circ}C$. The pixel size in our panel is $150{\mu}m{\times}150{\mu}m$, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.