• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.44-49
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• 2022

In this paper, we investigated current (I)- and voltage (V)-sweeping properties in a double-stack structure, Ge₂Sb₂Te₅/Ti/W-doped Ge₈Sb₂Te₁₁, a candidate medium for applications to multilevel phase-change memory. 200-nm-thick and W-doped Ge₂Sb₂Te₅ and W-doped Ge₈Sb₂Te₁₁ films were deposited on p-type Si(100) substrate using magnetron sputtering system, and the sheet resistance was measured using 4 point-probe method. The sheet resistance of amorphous-phase W-doped Ge₈Sb₂Te₁₁ film was about 1 order larger than that of Ge₂Sb₂Te₅ film. The I- and V-sweeping properties were measured using sourcemeter, pulse generator, and digital multimeter. The speed of amorphous-to-multilevel crystallization was evaluated from a graph of resistance vs. pulse duration (t) at a fixed applied voltage (12 V). All the double-stack cells exhibited a two-step phase change process with the multilevel memory states of high-middle-low resistance (HR-MR-LR). In particular, the stable MR state is required to guarantee the reliability of the multilevel phase-change memory. For the Ge₂Sb₂Te₅ (150 nm)/Ti (20 nm)/W-Ge₈Sb₂Te₁₁ (50 nm), the phase transformations of HR→MR and MR→LR were observed at t<30ns and t<65ns, respectively. We believe that a high speed and stable multilevel phase-change memory can be optimized by the double-stack structure of proper Ge-Sb-Te films separated by a barrier metal (Ti).

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.369-375
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• 1997

$V_{2}O_{5}/ThO_{2}/Pd$-doped $SnO_{2}$ sensor has a good selectivity and stability to CO at high sensor temperature of about $500^{\circ}C$, and shows rapid response. In particular, many kinds of interference gases, such as $NO_{x}$, $C_{3}H_{8}$, $CH_{4}$ and $SO_{2}$ have been found to give only a slight influence on the sensor selectivity to CO gas sensitivity by doped $V_{2}O_{5}$ (3.0 wt.%). For the sensor we used well-known thick film technological route with $V_{2}O_{5}$(3.0 wt.%), Pd(1.0 wt.%) and $ThO_{2}$(l.5 wt.%) as catalytic materials. In the case of mixed $NO_{x}$-CO gases, as combustion exhaust gas, only CO detection by $SnO_{2}$ type semiconductor sensor is generally very difficult because of $NO_{x}$ interference. The developed sensors can use to measure the exhausting gas of the automobile or the boiler for the Air-to-Fuel ratio control.

• The Journal of Korean Society for Radiation Therapy
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• v.26 no.2
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• pp.355-362
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• 2014

Purpose : When head&neck cancer radiation therapy, thermoplastic mask is applied for patients with fixed. The purpose of this study is to evaluate usefulness of thermoplastic mask for SRS in tomotherapy by conparison with the conventional mask. Materials and Methods : Typical mask(conventional mask, C-mask) and mask for SRS are used to fix body phantom(rando phantom) on the same iso centerline, then simulation is performed. Tomotherapy plan for orbit and salivary glands is made by treatment planning system(TPS). A thick portion and a thin portion located near the treatment target relative to the mask S-mask are defined as region of interest for surface dose dosimetry. Surface dose variation depending on the type of mask was analyzed by measuring the TPS and EBT film. Results : Surface dose variation due to the type of mask from the TPS is showed in orbit and salivary glands 0.65~2.53 Gy, 0.85~1.84 Gy, respectively. In case of EBT film, -0.2~3.46 Gy, 1.04~3.02 Gy. When applied to the S-mask, in TPS and Gafchromic EBT3 film, substrantially 4.26%, 5.82% showed maximum changing trend, respectively. Conclusion : To apply S-mask for tomotherapy, surface dose is changed, but the amount is insignificant and be useful when treatment target is close critical organs because decrease inter and intra fractional variation.

• Journal of the Korean Ceramic Society
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• v.39 no.2
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• pp.120-125
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• 2002

AC powder EL devices were fabricated by screen printing method with the dielectric materials in insulating layer and the electrical resistivity of rear electrode. Brightness and current density were measured at voltage range of 50∼300 $V_{rms}$ to estimate optoelectrical properties of AC powder EL devices, respectively. Frequency generator was used as system producing frequency and voltage of a sine wave. Brightness and current density were measured by luminometer and multimeter. Also, dielectric constant for dielectric layer was measured by impedance analyser after preparing thick film. Dielectric constant was improved with amount of $TiO_2$ to $BaTiO_3$ powder. By applying such a process to dielectric layer of low cost AC powder EL device, brightness was improved to 50 cd/$m^2$ at similar current density. Dielectric constant $BaTiO_3$ powder by solution combustion process is better than commercial $BaTiO_3$ powder. By applying to that of low power consumption AC powder EL device, brightness was improved to 85 cd/$m^2$. Brightness of AC powder EL device was relatively decreased by control of electrical resistivity of rear electrode, current density was also decreased.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Textile Coloration and Finishing
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• v.5 no.4
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• pp.29-41
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• 1993

In order to surface Hydrophobilization of Poly(ethylene terephthalate) (PET) fiber samples were treated in the atmosphere of CF$_{4}$ or $C_{2}$F$_{6}$glow discharge. The sample used in this study was PET film which is 75$\mu$m thick made by Teijin, O-Type(Japan). The cleaned samples were placed in plasma reactor made of pyrex glass cylinder, and plasma processing was carried out by glow discharge of CF$_{4}$ or $C_{2}$F$_{6}$ gas, being continuously fed by gas flow and continuously pumped out by a vacuum system. Electric power source for generate plasma state was sustained alternating current(60Hz) and voltage was sustained 600 volt. The duration of plasma treatment varied from 15 to 120 seconds except special case, the monomer gase pressure varied from 0.02 to 0.3 Torr and power range was 10 to 90 watts. The hydrophobic features of changed PET surface were evaluated by contact angle measurement and surface chemical characteristics were analyzed by ESCA. Results can be summerized as follows. 1. The most favorable setting position of substrate was the center area between the two electrodes. 2. $C_{2}$F$_{6}$ discharge current was lower than that of CF$_{4}$ when same voltage was sustained. Treated efficiency between CF$_{4}$ and $C_{2}$F$_{6}$ did not revealed significant differences under same electric power(wattage). 3. When monomer pressure is very low below 0.02 torr, as though substrate is exposed to CF$_{4}$ or $C_{2}$F$_{6}$ plasma, it tend to be hydrophilic through a little of fluorine bond and a great deal of oxidizing reaction. 4. There brought good hydrophobilization when monomer pressure was more 0.1 torr and duration of glow discharge treatment was over 45 seconds. When monomer pressure was too high, discharge current became low. Although prolong the duration, there was no more high hydrophobilization. 5. According to ESCA analysis, there were a little CF bond and a prevailing CF$_{2}$ bond in CF$_{4}$-treated substrate. There were CF$_{3}$, a little CF and a prevailing CF$_{2}$ bond in $C_{2}$F$_{6}$-treated substrate.d substrate.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.