• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.83-92
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• 2004

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.