• Journal of the Korean Society of Costume
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• v.59 no.9
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• pp.16-25
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• 2009

The purpose of this study is to develop pattern of a Upper Garment Prototype for late elementary school aged girls. The body of late elementary school aged girls changes steadily up to the adult and is characterized by its periodic noticeable physical distinctions. This study is selected a test pattern from 3 existing patterns through a preliminary wearing test, conducted wearing tests, and sensory evaluations three times to review and improve the pattern, and presented the pattern of late elementary school aged girls. The research pattern was developed considering aesthetic and functional aspect. The average score of sensory evaluation on appearance was 4.13 for the research pattern, which was higher than 2.74 for the test pattern. The according to the results of verifying significant differences in the test items between the two patterns through the t-test, in the items such as pleats in the line of a waist, the ease of the girth of a waist, the location of shoulder line was superior to the test pattern. The average score of the sensory evaluation on functionality was 4.91 for the research pattern, which was higher than 3.90 for the test pattern. The research pattern is superior to the test pattern in static posture, dynamic posture than the test pattern.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2008-2014
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• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.5 no.1
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• pp.42-49
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• 1987

This paper describes test-pattern generation and it;s sequence for fan out-free Combinational logic network with multiple faults. The method for detecting multiple faults, in systematic way, is established by using characteristic graphs. This method is applied even in the case of fan out-reconvergent combinational logic networks. In this case, the network is decomposed into a set of fan out-free sybnetworks so as to use the characteristic graphs, and minimal test patterns are generated seperately. The each test set is combined and the test pattern for fan out-reconvergent networks are derived. According to corresponding characteristic graph, additional test patterns to detect multiple faults are simply derived.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.3
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• pp.1-6
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• 1976

In this paper, a method of test pattern generation for the functional failure in both combinational and sequentlal logic networks by using exterded Boole an difference is proposed. The proposed technique provides a systematic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function that represents the Logic network for which the test patterns are to be generated. The computer experimental results show that the proposed method is suitable for both combinational and asynchronous sequential logic networks. Suitable models of clocked flip flops may make it possible for one to extend this method to synchronous sequential logic networks.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1065-1068
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• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.

• Journal of The Korean Society of Integrative Medicine
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• v.12 no.2
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• pp.55-63
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• 2024

Purpose : The purpose of this study is to determine the effects of scapula and pelvis symmetrical reciprocal pattern exercise of PNF concept on respiratory function and quality of life in elderly subjects. Methods : Nineteen elderly subjects with healthy were recruited. Subjects performed scapula and pelvis symmetrical reciprocal pattern exercise of PNF concept. Exercise was appied 30 minutes three times per week for four weeks. The respiratory function and quality of life (QOL) test three times (before, two weeks, and four weeks). Respiratory function includes forced vital capacity (FVC), forced expiratory volume at one second (FEV₁), Peak Expiratory Flow (PEF) and chest cage expansion test (CCET). The QOL test was measured Korean WHOQOL-BRIEF. The analysis method was analyzed through the one-way ANOVA repeated methods, and the statistical significance is α=.05. It was analyzed through the post test Bonferroni test. Results : After the 4 week scapula and pelvis symmetrical reciprocal pattern exercise of PNF concept showed statistically significant differences in the respiratory function (FVC, FEV₁, PEF, and CCET), and QOL (p<.05). As a result of the post-hoc test, FVC showed a significant increase in the mid test and post test compared to the pre test (p<.05), FEV₁ showed a significant increase in the post test compared to the pre test (p<.05). PEF showed a significant increase in all pre-test, mid-test, and post-test sections (p<.05), CCET showed a significant increase in all pre-test, mid-test, and post-test sections (p<.05). QOL showed a significant increase in all pre-test, mid-test, and post-test sections (p<.05). Conclusion : In this study, the scapula and pelvis symmetrical reciprocal pattern exercise of PNF concept improved respiratory function and QOL. The findings suggest that this intervention could be beneficial in improving respiratory function and QOL in the elderly.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.99-104
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• 1998

In this paper I designed test pattern generator which will be completely detected the faults of multi-stage Logic Circuit. 1 generated this pattern using the test pattern generation Logic Circuit. The generated test patterns compared with the exhausted testing was decreased pattern. This test pattern generator will detect the all single stuck-at faults in the multi-stage Logic Circuit. The choice of which of the many I.C testing methods to use can have a effect on the success or failure of the fault detected. One of the most important considerations is cost and designed test pattern generator is very low cost type.