• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.65-72
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• 1991

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1065-1068
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• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

• The KIPS Transactions:PartD
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• v.16D no.3
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• pp.371-380
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• 2009

Recently, lots of research on automated test data generation has been actively done. However, techniques for automated test data generation presented so far have been proved ineffective for programs with flag variables. It can present problems when considering embedded systems such as engine controllers that make extensive use of flag variables to record state information concerning devices. This paper introduces a technique for generating test data effectively for programs with flag variables. The presented technique transforms the test data generation problem into a SAT(SATisfiability) problem and makes advantage of SAT solvers for automated test data generation(ATDG). For the ends, we transform a program under test into Alloy which is the first-order relational logic and then produce test data via Alloy analyzer.

• Journal of KIISE:Software and Applications
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• v.37 no.12
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• pp.882-891
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• 2010

Many automated dynamic test data generation technique have been proposed. The techniques evaluate fitness of test data through executing instrumented Software Under Test (SUT) and then generate new test data based on evaluated fitness values and optimization algorithms. Previous researches and experiments have been showed that these techniques generate effective test data. However, optimization algorithms in these techniques incur much time to generate test data, which results in huge test case generation cost. In this paper, we propose a technique for reducing the time of evaluating a fitness of test data among steps of dynamic test data generation methods. We introduce the concept of Fitness Evaluation Program (FEP), derived from a path constraint of SUT. We suggest a test data generation method based on FEP and implement a test generation tool, named ConGA. We also apply ConGA to generate test cases for C programs, and evaluate efficiency of the FEP-based test case generation technique. The experiments show that the proposed technique reduces 20% of test data generation time on average.

• Educational Technology International
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• v.23 no.2
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• pp.157-181
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• 2022

Scale scores for cognitive domains have been used as an important indicator for both academic achievement and clinical diagnosis. For example, in education, Cognitive Abilities Test (CogAT) has been used to measure student's capability in academic learning. In a clinical setting, Cognitive Impairment Screening Test utilizes items measuring cognitive ability as a dementia screening test. We demonstrated a procedure of generating cognitive ability test items similar as in CogAT but the theory associated with the generation is totally different. When creating cognitive test items, we applied automatic item generation (AIG) that reduces errors in predictions of cognitive ability but attains higher reliability. We selected two cognitive ability test items, categorized as a time estimation item for measuring quantitative reasoning and a paper-folding item for measuring visualization. As CogAT has widely used as a cognitive measurement test, developing an AIG-based cognitive test items will greatly contribute to education field. Since CLASS is the only LMS including AIG technology, we used it for the AIG software to construct item models. The purpose of this study is to demonstrate the item generation process using AIG implemented within CLASS, along with proving quantitative and qualitative strengths of AIG. In result, we confirmed that more than 10,000 items could be made by a single item model in the quantitative aspect and the validity of items could be assured by the procedure based on ECD and AE in the qualitative aspect. This reliable item generation process based on item models would be the key of developing accurate cognitive measurement tests.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.