• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.52-55
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• 1996

This paper describes the bending traveling-wave type ultrasonic motor which generates the traveling wave by combining two standing waves with phase difference time and space. In $+20^{\circ}C$~$30^{\circ}C$, the USM motor operation character has represented normal condition. But the other temperature, (that is say, when long time operating condition) USM operation characteristic has abnormal condition, that is driving frequency, drive current and r.p.m is down. The recent USM has controller without temperature compensation. This study aimed at fuzzy controller which must follow the phase angle difference 90$^{\circ}$at operation temperature and them r.p.m and torque increase.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.65-68
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• 2001

In the vector control methods of induction motor, the stator current is divided into the flux and torque component current. By controlling these components respectively, the methods control independently flux and torque as in the DC motor and improve the control effects. To apply the vector control methods, the position of the rotor current is identified. The indirect vector control use the parameters of the machine to identify the position of rotor flux. But due to the temperature rise during machine operation, the variation of rotor resistance degrades the vector control. To solve the problem, the q-axis is aligned to reference frame without phase difference by comparing the real flux component with the reference flux component. Then to compensate the slip, PI controller is used. The proposed method keeps a constant slip by compensating the gain of direct slip frequency when the rotor resistance of induction motor varies. To prove the validations of the proposed algorithm in the paper, computer simulations is executed.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.153-159
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• 2012

In photovoltaic system, the characteristic of photovoltaic module such as open circuit voltage and short circuit current will be changed because of cell temperature and solar radiation. Therefore, a boost converter of the PV system connects between the output of photovoltaic system and DC link capacitor of grid connected inverter as controlling duty ratio for maximum power point tracking(MPPT). This paper shows the dynamic characteristic of the boost converter by comparing single-loop control algorithm and two-loop control algorithm using both analog and digital control. The proposed both compensation method has been verified with computer simulation and simulation results obtained demonstrate the validity of the proposed control schemes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.27-31
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• 1996

In this paper, The SSPA(Solid State Power Amplifier) is 100 watts amplifier which is used with C-Band Satellite communication Up-Link frequency, 5.875 ∼6.425 GHz. SSPA requires more output power than is available from a single GaAs FET with result it is necessary to combine the output of many device. To achieve a high power, it is important to make a good N-way power divider which has a small different phase, good combining efficiency and high power handling capability. The reliability of Power GaAs FET decrease with increasing junction temperature, power amplifier in general dissipate amount of power. It is important to provide them with a heatsink and a temperature compensation circuit to dispose of the unwanted heat. To compensate temperature, Using PIN diode attenuator, it is enable to get a precision gain control. The output power of the SSPA is more than 100 watt with which the TWTA (Traveling-Wave Tube Amplifier) can be replaced. Each stage was measured by the Network analyzer PH8510C, Power meter Booton 42BD, The gain is more than 53 dB, flatness is less than 1.5 dB.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.11-11
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• 2008

ZnO has a very large exciton binding energy (60 meV) as well as thermal and chemical stability, which are expected to allow efficient excitonic emission, even at room temperature. ZnO based electronic devices have attracted increasing interest as the backplanes for applications in the next-generation displays, such as active-matrix liquid crystal displays (AMLCDs) and active-matrix organic light emitting diodes (AMOLEDs), and in solid state lighting systems as a substitution for GaN based light emitting diodes (LEDs). Most of these electronic devices employ the electrical behavior of n-type semiconducting active oxides due to the difficulty in obtaining a p-type film with long-term stability and high performance. p-type ZnO films can be produced by substituting group V elements (N, P, and As) for the O sites or group I elements (Li, Na, and K) for Zn sites. However, the achievement of p-type ZnO is a difficult task due to self-compensation induced from intrinsic donor defects, such as O vacancies (Vo) and Zn interstitials ($Zn_i$), or an unintentional extrinsic donor such as H. Phosphorus (P) doped ZnO thin films were grown on c-sapphire substrates by radio frequency magnetron sputtering with various Ar/ $O_2$ gas ratios. Control of the electrical types in the P-doped ZnO films was achieved by varying the gas ratio with out post-annealing. The P-doped ZnO films grown at a Ar/ $O_2$ ratio of 3/1 showed p-type conductivity with a hole concentration and hole mobility of $10^{-17}cm^{-3}$ and $2.5cm^2/V{\cdot}s$, respectively. X-ray diffraction showed that the ZnO (0002) peak shifted to lower angle due to the positioning of $p^{3-}$ ions with a smaller ionic radius in the $O^{2-}$ sites. This indicates that a p-type mechanism was due to the substitutional Po. The low-temperature photoluminescence of the p-type ZnO films showed p-type related neutral acceptor-bound exciton emission. The p-ZnO/n-Si heterojunction LEO showed typical rectification behavior, which confirmed the p-type characteristics of the ZnO films in the as-deposited status, despite the deep-level related electroluminescence emission.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.