• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.4
• /
• pp.1059-1067
• /
• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.4
• /
• pp.123-128
• /
• 1994

Hardware realization of a digital 2-D homomorphic filter for real time contrast enhancement of video signal is presented. In homomorphic filter, logarithmic and exponential conversion used the memory lookup table method and because the hardware is implemented by multiplierless TTL devices, it can be designed to specific IC. The contrast gain can be controlled externally and the transfer function of homomorphic filter can be easily varied by the change of lookup table memory data.

• Journal of Korea Multimedia Society
• /
• v.12 no.5
• /
• pp.717-727
• /
• 2009

P2P (Peer-to-Peer) network depends on cooperation of peers considerably. However, some peers do not share files at all and only download files. Peers also share low quality files or unpopular files. These selfish behavior of peers is referred to 'free riding'. The free riding of peer may decrease participation of other peers or the system performance. In this paper, we propose an incentive mechanism, called IcMFS (Incentive Mechanism for File Sharing System), which provides the correct use of incentive mechanism using trust peer, computes contribution values referring behavior of peers and rewards peers. The proposed mechanism assigns bandwidth and TTL(Time-To-Live) to a peer and differentiates the use of service. A case study on simulations shows the service differentiation according to the contribution value of peer, the correct use of incentive mechanism using trust peer and the advantage by use of trust peer. To prove the stability of proposed mechanism, we also show the disadvantage that a peer receives from the incorrect use of incentive mechanism.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.7 no.2
• /
• pp.47-54
• /
• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.1A
• /
• pp.47-53
• /
• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.39 no.7
• /
• pp.757-764
• /
• 1990

The purpose of this study is to process binary images of Breadth First Linear Quadtree in hardware. Inthis paper, we designed and verified logic level circuit of ASIC for the encoding part of the binary image that is to convert the binary image into the representation of the Breadth First Linear Quadtree. The logic level circuit is composed of cells in TTL library. The significance of thes study is to implement an algorithm by hardware rather than by software, so that the processing time can be reduced by about 20 times.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.2
• /
• pp.10-17
• /
• 1989

The Berlekamp-Massey algorithm, the method of using the Euclid algorithm, and Fourier transforms over a finite field can be used for the decoding of Reed-Solomon codes (called RS codes). RS codes can also be decoded by the algorithm that was developed by Peterson and refined by the Gorenstein and Zierler. However, the decoding of RS codes using the Peterson-Gorenstein-Zieler algorithm offers sometimes computational or implementation advantages. The decoding procedure of the double-error correcting (31,27) Rs code over the symbol field GF ($2^5$) will be analyized in this paper. The complete analysis, gate array design, and implementation for encoder/decoder pair of (31.27)RS code are performed with a strong theoretical justification.