• Proceedings of the KIEE Conference
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• 1998.07c
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• pp.1125-1127
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• 1998

Inchon International Airport(IIA) is constructed for Northeast Asia Gate as is important for IIA to become a 21 century's leader in the world. as is planned for open at December 2000 as a important economic link for unified korea. Power System is designed through investigation of advanced domestic and international example. In addition to power facility operation it is designed for using an information infrastructure of whole airport. IIA Power System Design make instantaneously the Power Distribution Facilities and the SCADA System to construct the airport. and the Airport Power Information System to operate the Power System. It is designed to take efficient and safe Power System including the advanced technology. Power System make the integrated Power Information Database to operate the Main Control Center, analyze the data about the relation of the Power System and Airport operation, and will support the important files in the future.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.85-90
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• 2002

$RuO_2$/GaN and related contacts were investigated for Schottky contacts in GaN-Based optical and electronic devices. We demonstrated that an $RuO_2$ film forms a stable Schottky contact on a GaN layer with a barrier height (${\Phi}_B$) of 1.46 eV and transmittance of 70% in the visible and near UV region. $RuO_2$/GaN Schottky diode showed a breakdown at over -50V and leakage current of only 0.3 nA at -5V. The $RuO_2$/GaN Schottky type photodetector had the UV/Visible rejection ratio of over $10^5$ and the responsivity of 0.23 A/W at 330 nm. The $RuO_2$ gate AlGaN/GaN EFET exhibited high drain current ($I_d$) of 689.3 mA/mm and high transconductance ($g_m$) of 197.4 mS/mm. Cut-Off frequency ($f_t$) and maximum operating frequency ($f_{max}$) were measured as 27.0 GHz and 45.5 GHz, respectively.

• KIEAE Journal
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• v.10 no.5
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• pp.13-22
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• 2010

The old city centers of local metropolitans have lost their functions as CBD in korea. Those old city centers have an only role as a gate connected to the new CBD. This study aims to present regeneration stratigies of old city centers through Osaka case study. This research has been focused on the physical and environmental factors in urban regeneration. There are 4 strategies for old city centers. First, the strategy to attract people to the old city centers is high-density and mixed-use development having functions like shopping, entertainment, residence. This kind of development makes local metropolitan cities compact cities to protect urban sprawl. Second, strategy to give old city centers an identity is to conserve traditional culture and structures and to revitalize retail market. Third is to make pedestrian-friendly street system. Osaka ism't pedestrian friendly but remodelling the connect the pedestrian path to the culture facilities. Fourth is to have water and green environment. Green space is the strong factor that pull people to old city centers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1169-1171
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• 2003

This paper presents a 1.6[kW]class single phase high power factor(HPF) pulse width modulation(PWM) boost rectifier featuring soft commutation of the active switches at zero current. It incorporates the most desirable properties of conventional PWM and soft switching resonant techniques. The input current shaping is achieved with average current mode control and continuous inductor current mode. This new PWM converter provides zero current turn on and turn off of the active switches, and it is suitable for high power applications employing insulated gate bipolar transistors(IGBT'S). The principle of operation, the theoretical analysis, a design example, and experimental results from laboratory prototype rated at 1.6[kW] with 400[Vdc] output voltage are presented. The measured efficiency and the power factor were 96.2[%] and 0.99[%], respectively, with an input current Total Harmonic Distortion(THD) equal to 3.94[%], for an input voltage with THD equal to 3.8[%], at rated load.

• Journal of Korean Society of Rural Planning
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• v.18 no.3
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• pp.67-76
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• 2012

The purpose of this study is to analyze the landscape preference and landscape images of the Agricultural Aqueduct Bridges(AAB) by several different criteria. Semantic Differential Scale(SD scale) with landscape adjectives and landscape preference are used to estimate the alternatives of the AAB. The statistic methods such as descriptive analysis, t-test, factor analysis and regression, cluster analysis, are operated. The landscape preference of the alternatives is generally positive, 3.977 out of 7.000. The gate type is the most preferred, but the road-along type is the worst, by the location types. The simple repair type is the worst preferred, but total remodeling is the most, by the repair types. The characteristics of the AAB are analyzed and 4 factors of visual landscape are contracted; interest, orderliness, naturality and spatiality. Cumulative factor loading of these factors is about 65%, which is quite high. The higher and bigger AAB's are preferred, and the advanced finishing materials are also preferred, such as aluminum or wood panels. The long span is also preferred and the high repair cost would be preferred. But in this study, the cost-benefit analysis is not included, so it is recommended to research further, considering the cost variable with the visual factors.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.416-419
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• 1995

An analysis of a new load resonant inverter considering stray inductance is given. There are several different types for load resonant inverters. They can offer zero turn-on as well as zero turn-off switching losses, yielding high efficiency at high power and high frequencies. However, they didn't consider the influences of stray inductance. In conventional topology using lossless snubber capacitor, stray inductances result in very high frequency resonant current. Especially, these influences can be problematic in high power system such as induction heating system with large current of some 10A associated with it. These currents increase EMI problem, give harmful effects in gate driver's operation and increase loss of dc-link capacitor as well as snubber capacitor. Therefore, the effect of stray inductances should be treated and reduced. This paper presents a new load resonant inverter topology, which can reduce the effect of stray inductances.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.