• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1055-1063
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• 1999

공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다.Abstract The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.66-72
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• 2003

An ordinary differential equation in analytical numerics is utilized to some applications, for example, physics, mechanical engineering, electrical engineering, thermodynamics and etc. But this equation has problems a lots to process in the real time processing by software method. This paper is proposed a systolic Arrays architecture for solving the Runge-Kutta method. it is one of method for solving an ordinary differential equation. the proposed its architecture is very high speed and regular. this hardware proposed in this paper may be part of the mathematical problem solver's tool kit in the future and may be available to many applications in the engineering.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.1-9
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• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.245-248
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• 2001

본 논문에서는 연집 오류(burst error)에 우수한 정정 능력을 보이는 고속 RS(Reed-Solomon) 복호기를 제안한다. 제안된 RS 복호기는 RS(n, k, t); (37 < n ≤ 255, 21 < k ≤ 239, t = 8)의 사양을 지원하며 수정 유클리드 알고리즘(modified Euclid´s algorithm)을 이용한 시스톨릭 어레이(systolic array) 방식의 병렬처리 구조로 설계되었다. 고속 RS 복호기의 효율적인 VSLI 설계를 위하여 새로운 방식의 수정 유클리드 알고리즘 연간 회로를 제안한다. 제안된 수정 유클리드 알고리즘 회로는 2t + 1의 연산 지연 시간을 갖으며 기존 구조의 연산 지연 시간인 3t + 37에 비하여 t = 8 인 경우 약 72%의 연산 지연이 감소하였다. 제안된 구조를 VHDL을 이용하여 설계하였으며 SAMSUNG 0.5㎛(KG80) 라이브러리를 이용하여 논리 합성과 타이밍 검증을 수행하였다. 합성된 RS 복호기의 총 게이트 수는 약 77,000 개이며 최대 80MHz의 동작 속도를 나타내었다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1503-1506
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• 1987

This paper proposes the self test method for 16 point FFT processor with systolic array architecture. To test efficiently and solve the increased hardware problems due to built-in self test, we change the normal registers into Linear Feedback Shift Registers(LFSR). LFSR can be served as a test pattern generator or a signature analyzer during self test operation, while LFSR a ordering register or a accumulator during normal operation. From the results of logic simulation for 16 point FFT processor by YSLOG, the total time is estimated in about. 21.4 [us].

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.1-11
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• 1994

In computer graphics since objects atre constructed by lines and curves, the high-speed curve generator is indispensible for computer aided design and simulatation. Since the functions of graphic generation can be represented as a series of matrix operations, in this paper, two kind of the high-speed Bezier curve generator that uses matrix equation and a recursive relation for Bezier polynomials are designed. And B-spline curve generator is designed using interdependence of B-spline blending functions. As the result of the comparison of designed curve generator and reference [5], [6] in the operation time and number of operators, the curve generator with 1-dimensional systolic array processor for matrix vector operation that uses matrix equation for Bezier curve is more effective.