• 제목/요약/키워드: System-on-chip

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외경선삭가공시 등가유효경사각에 따른 칩절단 특성 (Chip Breaking Characteristics Depending on Equivalent Effective Rake Angle in Turning)

  • 이영문;장승일;손정우;윤종훈
    • 한국기계가공학회지
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    • 제3권2호
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    • pp.25-31
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    • 2004
  • Machinability in metal cutting processes depends on cutting input conditions such as cutting velocity, feed rate, depth of cut, types of work material and tool shape factors. In this study, to assess chip breaking characteristics of a turning process, an equivalent oblique cutting system to this has been established. And the equivalent effective rake angle was determined using side rake angle, back rake angle and side cutting edge angle of the tool. A non-dimensional parameter, Chip breaking index(CB), was used to assess Chip breaking characteristics of chip in conjunction with the equivalent effective rake angle. In case of positive rake angles of the equivalent effective rake, the back rake angle has little effect on the chip breaking characteristics however, in case of negative ones, the side rake angle has some effect on Chip breaking characteristics.

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SOC(System-On-a-Chip)에 있어서 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트 (Efficient Test Data Compression and Low Power Scan Testing for System-On-a-Chip(SOC))

  • 박병수;정준모
    • 한국콘텐츠학회논문지
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    • 제5권1호
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    • pp.229-236
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    • 2005
  • System-On-a-Chip(SOC)을 테스트하는 동안에 요구되는 테스트 시간과 전력소모는 SOC내의 IP 코어의 개수가 증가함에 따라서 매우 중요하게 되었다. 본 논문에서는 수정된 스캔 래치 재배열을 사용하여 scan-in 전력소모와 테스트 데이터의 양을 줄일 수 있는 새로운 알고리즘을 제안한다. 스캔 벡터 내의 해밍거리를 최소화하도록 스캔 래치 재배열을 적용하였으며 스캔 래치 재배열을 하는 동안에 스캔 벡터 내에 존재하는 don't care 입력을 할당하여 저전력 및 테스트 데이터 압축을 하였으며 ISCAS 89 벤치마크 외호에 적용하여 모든 경우에 있어서 테스트 데이터를 압축하고 저전력 스캔 테스팅을 구현하였다.

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IEEE 1500 래퍼를 이용한 효과적인 AMBA 기반 시스템-온-칩 코아 테스트 (Efficient AMBA Based System-on-a-chip Core Test With IEEE 1500 Wrapper)

  • 이현빈;한주희;김병진;박성주
    • 대한전자공학회논문지SD
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    • 제45권2호
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    • pp.61-68
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    • 2008
  • 본 논문에서는 Advanced Microcontroller Bus Architecture(AMBA) 기반 System-on-Chip(SoC) 테스트를 위한 임베디드 코어 테스트 래퍼를 제시한다. IEEE 1500 과의 호환성을 유지하면서 ARM의 Test Interface Controller(TIC)로도 테스트가 가능한 테스트 래퍼를 설계한다. IEEE 1500 래퍼의 입출력 경계 레지스터를 테스트 패턴 입력과 테스트 결과 출력을 저장하는 임시 레지스터로 활용하고 변형된 테스트 절차를 적용함으로써 Scan In과 Scan Out 뿐만 아니라 PI 인가와 PO 관측도 병행하도록 하여 테스트 시간을 단축시킨다.

선삭가공시 절삭조건에 의한 Chip형태의 분류와 예측에 관한 연구 (A Study on the Classification and Prediction of the Chip Type under the Specified Cutting Conditions in Turning)

  • Sim, G.J.;Cheong, C.Y.;Seo, N.S.
    • 한국정밀공학회지
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    • 제12권8호
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    • pp.53-62
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    • 1995
  • In recent years, the rapid development of the machine tool and tough insert has made metal removal rates increase, and automatic system without human supervision requires a higher degree reliability of machining process. Therefore the control of chips is one of the important topics which deserves much attention. The chip classification was made based upon standard deviation of the mean cutting force measured by a tool dynamometer. STS304was chosen as the workpiece which is known as the difficult-to-cut material and mainly saw-toothed chip produced, and the chip type according to the standard deviation of mean cutting force was classified into five categories in this experiment. Long continuous type chip which interrupts the normal cutting process, and damages the operator, tool and workpiece has low standard deviation value, while short broken type chip, which is favourable chip for disposal, has relatively large standard deviation value. In addition, we investigated the possibility that the chip type can be predicted analyzing the relationship between chip type and cutting condition by the trained neural network, and obtained favourable results by which the chip type can be predicted with cutting conditon before cutting process.

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디지털 보호 계전기 전용 제어 칩 설계 (Design of digital relay controller on a single chip)

  • 서종완;정호성;권기백;서희석;신명철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 A
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    • pp.215-217
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    • 2000
  • Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

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QFN 반도체 패키지의 외형 결함 검사를 위한 효과적인 결함 분류 시스템 개발 (Development of an Effective Defect Classification System for Inspection of QFN Semiconductor Packages)

  • 김효준;이정섭;주효남;김준식
    • 융합신호처리학회논문지
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    • 제10권2호
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    • pp.120-126
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    • 2009
  • 반도체 외관결함에는 발생 요인이 각각 다른 crack, foreign material, chip-out, chip, void 등이 있으며, 검사 시스템에서는 결함 유무 및 결함 분류를 수행하여 효과적인 공정관리가 가능하여야 한다. 본 논문에서는 QFN 패키지 결함의 분류를 위한 알고리즘 및 광학시스템을 제안한다. 제안한 방법에서 분류가 어려운 결함 중 하나인 foreign material 과 chip의 효과적인 분류를 위해 제안한 결함의 위치, 밝기의 특징정보(feature)를 사용한 ML(Maximum Likelihood ratio) 분류방법 및 특징정보 획득에 효과적인 광학계를 제안하였다. 실험 결과에서 분류가 어려운 foreign material과 chip에 대한 신뢰성 높은 분류성능을 보였다.

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Real-time Sound Localization Using Generalized Cross Correlation Based on 0.13 ㎛ CMOS Process

  • Jin, Jungdong;Jin, Seunghun;Lee, SangJun;Kim, Hyung Soon;Choi, Jong Suk;Kim, Munsang;Jeon, Jae Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권2호
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    • pp.175-183
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    • 2014
  • In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

NoC에서의 저전력 테스트 구조 (Power-aware Test Framework for NoC(Network-on-Chip))

  • 정준모;안병규
    • 한국산학기술학회논문지
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    • 제8권3호
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    • pp.437-443
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    • 2007
  • 본 논문에서는 임베디드 프로세서 및 네트워크 구조를 기반으로 구성된 NoC(Network-On-Chip)의 저전력 테스트 구조를 제안한다. 임베디드 프로세서와 여러개의 코어로 구성된 네트워크 구조에 벤치마크 회로를 직접 연결하여 테스트 전력소모를 평가하였으며, 각 코어의 테스트 패턴을 저전력 소모가 되도록 매핑하여 테스트 전력소모를 감소시켰다. 또한 임베디드 프로세스 코어를 ATE(Automatic Test Equipment)로 사용하여 테스트 시간을 줄일수 있었다. ISCAS89 벤치마크 회로에 대해서 테스트 시간은 매우 효과적으로 감소되었으며 평균 전력소모는 약 8%가 감소되었다.

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대형 공작기계용 칩 처리시스템 설계 및 커터 해석 (Analysis of Cutter and Design of Chip Processing System for Large Scale Machine Tool)

  • 이종문;양영준
    • 한국기계가공학회지
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    • 제11권4호
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    • pp.147-153
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    • 2012
  • The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

칩마운터의 직진 테이프 피더 설계 및 평가 (Mechanical Design and Evaluation of Linear Tape Feeder for Chip Mounter)

  • 이수진;강성민;이창희;김용연
    • 한국정밀공학회지
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    • 제23권5호
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    • pp.155-161
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    • 2006
  • This paper introduces a new type of mechanical tape feeder for chip mounter. The mechanical feeder is composed of a pneumatic linear actuator and a linear feeding module with the application of a cam-slider. As semiconductor chips are getting smaller, PCB assembly makers require the feeder to position the chip with high accuracy. The linear feeding system improves the positioning accuracy of the chip by getting rid of the index error, which brings into existence on the sprocket rotating feeder. It also can make greatly reduce the dumping rate. The dumping error is caused by the impact occurred as the pawl to interrupt ratchet wheel rotation. The paper discusses its mechanism and mechanical performance. The positioning accuracy and the dynamic characteristic were measured for long time operation and analyzed. As a result, the feeder showed very good performance. However, the feeding system was dynamically unstable due to the cover film eliminator that is required to be modified