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  • Title/Summary/Keyword: System-on-Chip (SoC)

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Automatic Generation of GCP Chips from High Resolution Images using SUSAN Algorithms

  • Um Yong-Jo;Kim Moon-Gyu;Kim Taejung;Cho Seong-Ik
    • Proceedings of the KSRS Conference
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    • 2004.10a
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    • pp.220-223
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    • 2004
  • Automatic image registration is an essential element of remote sensing because remote sensing system generates enormous amount of data, which are multiple observations of the same features at different times and by different sensor. The general process of automatic image registration includes three steps: 1) The extraction of features to be used in the matching process, 2) the feature matching strategy and accurate matching process, 3) the resampling of the data based on the correspondence computed from matched feature. For step 2) and 3), we have developed an algorithms for automated registration of satellite images with RANSAC(Random Sample Consensus) in success. However, for step 1), There still remains human operation to generate GCP Chips, which is time consuming, laborious and expensive process. The main idea of this research is that we are able to automatically generate GCP chips with comer detection algorithms without GPS survey and human interventions if we have systematic corrected satellite image within adaptable positional accuracy. In this research, we use SUSAN(Smallest Univalue Segment Assimilating Nucleus) algorithm in order to detect the comer. SUSAN algorithm is known as the best robust algorithms for comer detection in the field of compute vision. However, there are so many comers in high-resolution images so that we need to reduce the comer points from SUSAN algorithms to overcome redundancy. In experiment, we automatically generate GCP chips from IKONOS images with geo level using SUSAN algorithms. Then we extract reference coordinate from IKONOS images and DEM data and filter the comer points using texture analysis. At last, we apply automatically collected GCP chips by proposed method and the GCP by operator to in-house automatic precision correction algorithms. The compared result will be presented to show the GCP quality.

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Design of Modified JTAG for Debuggers of RISC Processors (RISC 프로세서의 디버거를 위한 변형된 JTAG 설계)

  • Xu, Jingzhe;Park, Hyung-Bae;Jung, Seung-Pyo;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.65-75
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    • 2011
  • As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

Optimization of FPGA-based DDR Memory Interface for better Compatibility and Speed (호환성 및 속도 향상을 위한 FPGA 기반 DDR 메모리 인터페이스의 최적화)

  • Kim, Dae-Woon;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.12
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    • pp.1914-1919
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    • 2021
  • With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

MLC NAND-type Flash Memory Built-In Self Test for research (MLC NAND-형 Flash Memory 내장 자체 테스트에 대한 연구)

  • Kim, Jin-Wan;Kim, Tae-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.3
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    • pp.61-71
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    • 2014
  • As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

Design and Implementation of an Around-View Monitoring system of Smart User Interface based on Windows O/S (Windows 운영체제 기반 어라운드 뷰 모니터링 시스템의 스마트 사용자 인터페이스 설계 및 구현)

  • Cheon, Seung-hwan;Jang, Si-woong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.427-430
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    • 2012
  • 최근 차량용 블랙박스, 자동 운전 시스템, 어라운드 뷰 시스템 등과 같은 운전자의 편의와 안전을 위한 장치 및 시스템들이 개발되고 있다. 현재 운전자를 위한 보조 시스템으로 구글(google)의 자동 운전 시스템(Auto Car Driving System)과 현대 모비스(hyundai mobis)의 AVM 시스템(Around View Monitoring System) 등의 다양한 차량용 편의장치 시스템들이 등장했다. 위와 같은 다양한 ECU들을 관리하기 위한 서버 및 저장 장치 역할을 할 수 있는 고사양의 Car PC의 장착이 필수적이다. 기존의 AVM 시스템은 차량 주변을 실시간으로 제공하기 위해 임베디드 또는 별도의 차량용 네트워크를 통해 임베디드 시스템 또는 SoC(System On Chip)형태의 하드웨어 기반으로 개발되고 있다. 하지만 고사양의 Car PC 기반에서는 별도의 비용없이 소프트웨어로 구현이 가능하다. 본 논문에서는 차량의 전 후 좌 우에 장착된 4대의 카메라로부터 입력된 차량 주변 상황을 한눈에 보여주는 AVM 시스템(Around-View Monitoring System)을 위한 카메라 보정 및 정합 처리 모듈 및 AVM 시스템을 Windows를 O/S로 하는 PC 내부에서 기존의 AVM 시스템을 이용하여 화면에 전 후 좌 우 버튼을 각각 만들어 버튼을 터치했을 때, 각 버튼에 해당되는 영상이 AVM 시스템과 함께 출력되도록 하거나 디스플레이에 Full 버전으로 출력되도록 S-UI(Smart User Interface)를 설계 및 구현한다. 제안하는 AVM 시스템과 기존의 AVM 시스템의 성능과 기능을 비교 분석함으로써 제안하는 영상 처리 모듈을 이용하여 추가 비용이 발생하지 않는 AVM 시스템의 구현 가능성을 검증한다.

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Analyze Consumer Behavior through Prospect of Healthcare Market (소비자 행태 분석을 통한 헬스케어 시장 전망)

  • Gil, Hyun-Jin;Kim, Woo-bin;Lee, Jae-Bong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.513-516
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    • 2015
  • Healthcare industry is one of the rapidly increasing sphere from high technology IT products and wireless communication. In particular, increase in aging society korea and whole world peoples want to treat whenever and wherever rather than go to the hospital. Accordingly, and also brand new companies which has creative ideas are being founded nowadays. As the development of healthcare industry, many different kind of health care devices is being developed use internet of things. Therefore we are conducted a surveying aimed at healthcare customer and analyse the healthcare use trend and development direction in this dissertation.

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BER Improvement Correlation-Flattened Binary CDMA (상관도 평활화된 Binary CDMA의 BER 개선)

  • Seo, Keun-Jong;Chong, Min-Woo;Kim, Yong-Cheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.1C
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    • pp.9-17
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    • 2004
  • We present a performance improvement of Binary CDMA by flattening the correlation values. A Binary CDMA system, in which multi-leveled transmission signal of multi-code CDMA is clipped into a binary value, is cost-efficient since the strict linearity of the power amplifier is relieved. However, a loss of orthogonality among user channels due to the clipping causes the correlation values at the receiver to have a random distribution. If the correlation value for even a single channel goes too low, the average BER drops considerably. We developed a method of correlation flattening, where the binary chip pattern at the transmitter is adjusted so that the correlation values have averaged magnitude. Experimental results on several spreading codes show that the correlation flattening method increases the number of available channels at reduced BER.

A Study on Welding Performance Improvement of Inverter Arc Welding Machine using Instantaneous Output Current Control Method

  • Chae, Y.M.;Gu, J.Y.;Gho, J.S.;Mok, H.S.;Choe, G.H.;Won, C.Y;Kim, G.S.
    • Proceedings of the KIPE Conference
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    • 1998.10a
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    • pp.1012-1016
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    • 1998
  • According to the adoption of inverter circuit topology for welding machine area, the improvement of welding performance can be achieved. However conventional CO2 inverter arc welding machine uses the constant voltage characteristics. So the metal transfer is performed under unoptimum condition in the sence of spatter generation. In this paper the new control algorithm is proposed for welding machine, which is the instantaneous output current control method using single chip microprocessor. But the optimum waveform of welding current is still uncertain, as a first step for figuring out the optimized waveforms, this study was performed. And as a result of performance test of the proposed system, it was demonstrated that all of the waveform variation parameter could be set individually and the generated spatter is reduced compared to conventional inverter arc welding machine.

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Design of a Small Area 12-bit 300MSPS CMOS D/A Converter for Display Systems (디스플레이 시스템을 위한 소면적 12-bit 300MSPS CMOS D/A 변환기의 설계)

  • Shin, Seung-Chul;Moon, Jun-Ho;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.1-9
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    • 2009
  • In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with 0.13μm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26mm2 (510μm×510μm) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

Design of DVB-T/H SiP using IC-embedded PCB Process (IC-임베디드 PCB 공정을 사용한 DVB-T/H SiP 설계)

  • Lee, Tae-Heon;Lee, Jang-Hoon;Yoon, Young-Min;Choi, Seog-Moon;Kim, Chang-Gyun;Song, In-Chae;Kim, Boo-Gyoun;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.9
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    • pp.14-23
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    • 2010
  • This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is 8mm×8mm. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.