• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.3
• /
• pp.9-15
• /
• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.93-93
• /
• 2016

Large scale integrated circuits (LSIs) has been improved by the shrinkage of the circuit dimensions. The smaller chip sizes and increase in circuit density require the miniaturization of the line-width and space between metal interconnections. Therefore, an extreme precise control of the critical dimension and pattern profile is necessary to fabricate next generation nano-electronics devices. The pattern profile control of plasma etching with an accuracy of sub-nanometer must be achieved. To realize the etching process which achieves the problem, understanding of the etching mechanism and precise control of the process based on the real-time monitoring of internal plasma parameters such as etching species density, surface temperature of substrate, etc. are very important. For instance, it is known that the etched profiles of organic low dielectric (low-k) films are sensitive to the substrate temperature and density ratio of H and N atoms in the H2/N2 plasma [1]. In this study, we introduced a feedback control of actual substrate temperature and radical density ratio monitored in real time. And then the dependence of etch rates and profiles of organic films have been evaluated based on the substrate temperatures. In this study, organic low-k films were etched by a dual frequency capacitively coupled plasma employing the mixture of H2/N2 gases. A 100-MHz power was supplied to an upper electrode for plasma generation. The Si substrate was electrostatically chucked to a lower electrode biased by supplying a 2-MHz power. To investigate the effects of H and N radical on the etching profile of organic low-k films, absolute H and N atom densities were measured by vacuum ultraviolet absorption spectroscopy [2]. Moreover, using the optical fiber-type low-coherence interferometer [3], substrate temperature has been measured in real time during etching process. From the measurement results, the temperature raised rapidly just after plasma ignition and was gradually saturated. The temporal change of substrate temperature is a crucial issue to control of surface reactions of reactive species. Therefore, by the intervals of on-off of the plasma discharge, the substrate temperature was maintained within ${\pm}1.5^{\circ}C$ from the set value. As a result, the temperatures were kept within $3^{\circ}C$ during the etching process. Then, we etched organic films with line-and-space pattern using this system. The cross-sections of the organic films etched for 50 s with the substrate temperatures at $20^{\circ}C$ and $100^{\circ}C$ were observed by SEM. From the results, they were different in the sidewall profile. It suggests that the reactions on the sidewalls changed according to the substrate temperature. The precise substrate temperature control method with real-time temperature monitoring and intermittent plasma generation was suggested to contribute on realization of fine pattern etching.

• Journal of Technologic Dentistry
• /
• v.34 no.2
• /
• pp.95-103
• /
• 2012

Purpose: Fracture strength of all-ceramic 3-unit fixed partial dentures manufactured by CAD/CAM and copy-milling systems were evaluated. Methods: Zirconia cores were made by milling the pre-sintered zirconia block by CAD/CAM or copy milling method followed by subsequent sintering. By building-up the corresponding porcelains on the core, all-ceramic bridges were fabricated, and those were evaluated in comparison with PFM fixed partial denture. Results: During the flexural test of the 3-unit PFM bridge, the porcelain started to chip or break at 507.28(${\pm}62.82$)kgf and the metal framework did not break until the maximum load level of 800kgf which was set in the testing instrument of this study. However, among all-ceramic restoration test groups, Everest(EV) group showed a peeling off or breakage of the porcelain from 365.64(${\pm}64.96$)kgf and the core was broken at 491.77(${\pm}55.62$)kgf. Those values of Zirkonzahn(ZR) were 431.03(${\pm}58.47$)kgf and 602.74(${\pm}48.44$)kgf, respectively. The break strength of the porcelain of PFM(PM) group was significantly higher than that of EV (p<0.05) group and there was no significant difference when comparing to that of ZR (p>0.05). ZR group showed higher break strength than that of EV group however there was no significant difference (p>0.05). The break strength of cores were in the increasing order of EV < ZR < PM (p<0.05). Conclusion: We could find that even though the PM group fractured at much higher value than all-ceramic cores, the breakage values of the porcelain of PM group with crack formation or delamination, which will be regarded as clinical failure, was significantly higher than that of EV group and not significantly higher than that of ZR group at p-values of 0.05. The break strength of ZR group was higher than that of EV group at an insignificant level(p>0.05).

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.9
• /
• pp.68-73
• /
• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Society of Cosmetic Scientists of Korea
• /
• v.30 no.2
• /
• pp.147-151
• /
• 2004

This study aims at measuring electrical and rheological properties of cosmetic emulsions on the skin under shear flow. The effects of volume ratio and surfactants on structural changes of emulsions were examined by determining the changes of electrical resistance, viscosity, and morphology. As the ratio of the internal phase increased, the phase inversion occurred more quickly. The viscosity change was found to increase with increasing of the variation of electrical resistance of the emulsions. This phenomenon may be caused by decreased resistant force against the shear flow because of the breakdown of the internal phase. Surfactants a]so played a key ro]e on phase transition of emulsions. It is likely that polymeric surfactants anchoring on the emulsion surface reinforced the interfacial mechanical strength. As the concentration of surfactants increased, the phase transition occurred more slowly. It has been demonstrated that the phase changes of emulsions under shear flow can be monitored on the real-time basis by using a JELLI$\^$TM/ chip system, a combination of conductiometry and rheometry. Our approach is expected to a useful experimental tool for predicting the phase transition of the cosmetic products during skin application.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.122-130
• /
• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.11
• /
• pp.32-40
• /
• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.73-82
• /
• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of KIISE:Software and Applications
• /
• v.32 no.10
• /
• pp.1003-1012
• /
• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.58-67
• /
• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.