• Title/Summary/Keyword: System-Level Simulator

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High Level Design and Performance Evaluation for the Implementation of WCDMA Base Station Modem (WCDMA 기지국 모뎀의 구현을 위한 상위 레벨 설계 및 통합 성능 평가)

  • Do Joo-Hyun;Lee Young-Yong;Chung Sung-Hyun;Choi Hyung-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1A
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    • pp.10-27
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    • 2005
  • In this paper, we propose a high level design architecture of WCDMA(UMTS) base station modem and synchronization algorithms applied to the proposed architecture. Also analysis of each synchronization algorithm and performance evaluation of fixed point designed modem are shown. Since the target system is base station modem, each synchronization algorithm is designed for its stable operation. To minimize implementation complexity, optimum fixed point design for best operation of synchronization algorithms is performed. We performed symbol level link simulation with fixed point designed modem simulator for data rate of 12.2kbps, 64kbps, 144kbps, and 384kbps. We compared performance results to the minimum requirements specified in 3GPP TS 25.104(Release 5). Extensive computer simulation shows that the proposed modem architecture has stable operation and outperform the minimum requirement by 2 dB. The proposed modem architecture has been applied in the implementation of WCDMA reverse link receiver modem chip successfully.

Unified Design Methodology and Verification Platform for Giga-scale System on Chip (기가 스케일 SoC를 위한 통합 설계 방법론 및 검증 플랫폼)

  • Kim, Jeong-Hun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.106-114
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    • 2010
  • We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

Study on coexistence through interference evaluation between LTE and DTV in the UHF band (UHF대역에서 LTE와 DTV간 간섭 평가를 통한 공유 방안 연구)

  • Kim, Daejung;Chung, Kwangsue
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.4
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    • pp.805-814
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    • 2013
  • According to the shut-down of Analog TV service on 30th. December, 2012, UHF Digital Dividend Band (698~806MHz) could be used for Mobile service such as LTE(Long Term Evolution). In the condition that this band is allocated for LTE service, Interference evaluation between LTE and adjacent DTV service was carried out, using LTE-A system-level simulator which was developed for simulation of IMT-Advanced technology. If LTE service be commercialized in this band, this study proposes the coexistence condition through the interference evaluation such as the effects not only to DTV receiver from LTE terminal but also to LTE base station from DTV transmitter. It is expected that the coexistence condition by these studies will be applied to network algorism for IMT-Advanced system in this band.

Research on an Engagement Level Underwater Weapon System Model with Neyman-Pearson Detector (Neyman-Pearson 표적 탐지기를 적용한 수중 무기체계 교전수준 모델 개발 연구)

  • Cho, Hyunjin;Kim, Wan-Jin;Kim, Sanghun;Yang, Hocheol;Lee, Hee Kwang
    • Journal of the Korea Society for Simulation
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    • v.28 no.2
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    • pp.89-95
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    • 2019
  • This paper introduces the simulation concepts and technical approach of underwater weapon system performance analysis simulator, especially focused on probabilistic target detection concepts. We calculated the signal excess (SE) value using SONAR equation, then derived the probability density function(PDF) for target presence($H_1$) or absence($H_0$) cases, respectively. With the Neyman-Pearson detector criterion, we got the probability of detection($P_D$) while satisfying the given probability of false alarm($P_{FA}$). At every instance of simulation, target detection is decided in the probabilistic perspective. With the proposed detection implementation, we improved the model fidelity so that it could support the tactical decision during the operation.

3D feature profile simulation for nanoscale semiconductor plasma processing

  • Im, Yeon Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.61.1-61.1
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    • 2015
  • Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

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A Hardware-Software Co-verification Methodology for cdma2000 1x Compliant Mobile Station Modem (cdma2000 1x 이동국 모뎀을 위한 하드웨어-소프트웨어 동시 검증 방법)

  • Han, Tae-Hee;Han, Sung-Chul;Han, Dong-Ku;Kim, Sung-Ryong;Han, Geum-Goo;Hwang, Suk-Min;Kim, Kyung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.46-56
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    • 2002
  • In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.

Improvement of Fire Detection in Rack-type Warehouses using FDS (FDS를 이용한 랙크식 창고의 화재감지 개선에 관한 연구)

  • Choi, Ki-Ok;Park, Moon-Woo;Choi, Don-Mook
    • Fire Science and Engineering
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    • v.33 no.5
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    • pp.55-60
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    • 2019
  • The occurrence of fire in rack-type warehouses may either lead to the warehouses getting entirely burned up or collapsing. This can be attrubuted to the high height of rack-type warehouses, in which combustibles are generally vertically stacked. These characteristics make it difficult to detect a fire early; because detectors are installed on the ceiling, these fires cannot be extinguished at an early stage. In this study, the flow of heat and smoke generated by a fire in a rack-type warehouse was analyzed using a fire dynamic simulator. Through this analysis, the optimal installation conditions of fire detectors for the early detection of fire in rack-type warehouses were confirmed. The analysis results confirmed that complex detection of heat and smoke is required for the early detection of fire in rack type warehouses. Furthermore, it was found that fixed temperature detectors are not suitable for these warehouses, resulting in the need to install heat-smoke hybrid detectors at every three rack levels.

Customized Evacuation Pathfinding through WSN-Based Monitoring in Fire Scenarios (WSN 기반 화재 상황 모니터링을 통한 대피 경로 도출 알고리즘)

  • Yoon, JinYi;Jin, YeonJin;Park, So-Yeon;Lee, HyungJune
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.11
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    • pp.1661-1670
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    • 2016
  • In this paper, we present a risk prediction system and customized evacuation pathfinding algorithm in fire scenarios. For the risk prediction, we apply a multi-level clustering mechanism using collected temperature at sensor nodes throughout the network in order to predict the temperature at the time that users actually evacuate. Based on the predicted temperature and its reliability, we suggest an evacuation pathfinding algorithm that finds a suitable evacuation path from a user's current location to the safest exit. Simulation results based on FDS(Fire Dynamics Simulator) of NIST for a wireless sensor network consisting of 47 stationary nodes for 1436.41 seconds show that our proposed prediction system achieves a higher accuracy by a factor of 1.48. Particularly for nodes in the most reliable group, it improves the accuracy by a factor of up to 4.21. Also, the customized evacuation pathfinding based on our prediction algorithm performs closely with that of the ground-truth temperature in terms of the ratio of safe nodes on the selected path, while outperforming the shortest-path evacuation with a factor of up to 12% in terms of a safety measure.

Data Structure of a Program Generation and Managing Track Data for Smart Train Route Control (Smart열차진로제어를 위한 선로데이터 생성관리프로그램의 데이터 구조)

  • Yoon, Yong-Ki;Hwang, Jong-Gyu;Jo, Hyun-Jeong;Lee, Jae-Ho
    • Proceedings of the KIEE Conference
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    • 2007.04c
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    • pp.234-236
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    • 2007
  • Even though the existing train route controlling method, using track circuits, ensures the sufficient number of operation, it still has problems such as discordance between train numbers which was planned for operating and train numbers being operated on the track, and allowing only one train entering for one route. To solve those problems, we study and develop the Smart train route controlling system which uses the real-time informations of train positions. This system enables improve the coefficient of utilization in a certain train route controlling section, and the safety level of train route controlling, but we should ensure satisfying reliability of data about tracks operated by trains. In addition, there is a need to protect accidents caused by erroneous information of train position, by reflecting changes of tracks, for example maintenance, improvement, expansion of tracks. In this paper, we describes data structure of a developed program which required to change CAD files to wiring diagrams and to generate them to data of tracks. And we show the result that the simulator, using the data structure, controls speed and route of trains without problems.

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HYLGS 모델을 활용한 수도권 매립지에서의 침출수-가스의 동시유동 해석에 관한 연구

  • 이광희;박용찬;성원모
    • Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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    • 1998.11a
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    • pp.225-231
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    • 1998
  • Open dump causes groundwater and soil contamination by leachate, air pollution by LFG (Landfill Gas). In this paper, in order to improve landfill researches which have been done about reduction of high leachate level and LFG collection in the Kimpo landfill separately, the effect of simultaneous flowing of leachate and LFG has been Studied. The HYLGS (Hanyang Leachate Gas Simulator) used in this study is a 3D, 2-phase, transient FDM model which can be applied to venting trenches in a landfill. From present numerical analysis it can be concluded that all the pressures of the Kimpo landfill grid system are almost the same and their maximum value in the center grid block of the system is approximately 26 m $H_2O$ (2.52 atm), that because the pressures of venting trench layer situated in the middle of the landfill have the lowest values and equal with air pressure, the venting trenches play an important role in landfill stabilization, that the flow of gas will be more difficult as time goes by owing to the increase of LGR(Leachate and gas ratio).

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