• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.19 no.4
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• pp.469-477
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• 2021

Safe storage of spent nuclear fuel in deep underground repositories necessitates an understanding of the long-term alteration of metal canisters and buffer materials. A small-scale laboratory alteration test was performed on metal (Cu or Fe) chips embedded in compacted bentonite blocks placed in anaerobic water for 1 year. Lactate, sulfate, and bacteria were separately added to the water to promote biochemical reactions in the system. The bentonite blocks immersed in the water were dismantled after 1 year, showing that their alteration was insignificant. However, the Cu chip exhibited some microscopic etch pits on its surface, wherein a slight sulfur component was detected. Overall, the Fe chip was more corroded than the Cu chip under the same conditions. The secondary phase of the Fe chip was locally found as carbonate materials, such as siderite (FeCO₃) and calcite ((Ca, Fe)CO₃). These secondary products can imply that the local carbonate occurrence on the Fe chip may be initiated and developed by an evolution (alteration) of bentonite and a diffusive provision of biogenic CO₂ gas. These laboratory scale results suggest that the actual long-term alteration of metal canisters/bentonite blocks in the engineered barrier could be possible by microbial activities.

• Journal of IKEEE
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• v.23 no.1
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• pp.295-301
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• 2019

A heater in a portable real-time polymerase chain reaction(PCR) system is one of the important factors for controlling the PCR thermocycle precisely. Since heaters are integrated on a small-sized PCR chip for rapid heating and fabricated by semiconductor processes, the cost of producing PCR chips is high. Here, we propose to use chip resistors as an inexpensive and accurate temperature control method. The temperature distribution was simulated using one or two chip resistors on a real-time PCR chip and the PCR chip with uniform temperature distribution was fabricated. The temperature rise and fall rates were $18^{\circ}C/s$ and $3^{\circ}C/s$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• ETRI Journal
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• v.22 no.4
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2212-2215
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• 2003

In this paper, we proposed speech feature vector extractor for embedded system using TMS 320C31 DSP chip. For this extractor, we used algorithm using cepstrum coefficient based on LPC(Linear Predictive Coding) that is reliable algorithm to be is widely used for speech recognition. This system extract the speech feature vector in real time, so is used the mobile system, such as cellular phones, PDA, electronic note, and so on, implemented speech recognition.

• Current Optics and Photonics
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• v.5 no.2
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• pp.147-154
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• 2021

Microfluidic chip technology is a research focus in biology, chemistry, and medicine, for example. However, microfluidic chips are rarely applied in imaging, especially in ghost imaging. Thus in this work we propose a ghost-imaging system, in which we deploy a novel microfluidic chip modulator (MCM) constructed of double-layer zigzag micro pipelines. While in traditional situations a spatial light modulator (SLM) and supporting computers are required, we can get rid of active modulation devices and computers with this proposed scheme. The corresponding simulation analysis verifies good feasibility of the scheme, which can ensure the quality of data transmission and achieve convenient, fast ghost imaging passively.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.