• 제목/요약/키워드: System Level Design

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초고층 건물의 풍가속도응답 조절 기법 (Control Method of Wind Induced Vibration Level for High-rise buildings)

  • 김지은;서지현;박효선
    • 한국전산구조공학회:학술대회논문집
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    • 한국전산구조공학회 2005년도 춘계 학술발표회 논문집
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    • pp.375-382
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    • 2005
  • In this paper, a practical control method of wind-induced vibration of high-rise buildings is presented in the form of resizing algorithm. In the structural design process for high-rise buildings, the lateral load resisting system for the building is more often determined by serviceability design criteria including wind-induced vibration level. Even though many drift method have been developed in various forms, no practical design method for wind induced vibration has been developed so far. Structural engineers rely upon heuristic or experience in designing wind induced vibration. The performance of the proposed method is evaluated by comparing wind-induced vibration levels estimated both from approximate techniques and wind tunnel test.

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Trans-axle형태의 구동계를 갖는 지게차의 진동원 파악 및 저감설계 (Identification of vibration source and vibration improvement design of forklift truck with trans-axle type power train)

  • 박인환;김성재;김낙인
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2001년도 춘계학술대회논문집
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    • pp.855-860
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    • 2001
  • In this study, the improvement work to reduce the steering wheel vibration of a forklift truck is performed. The forklift truck newly developed possesses a trans-axle type power train to achieve a compact and low-price design. The forklift truck is directly subjected to a high-level engine vibration through hard mounted trans-axle housing. The engine vibration shakes the whole system of the forklift truck, and then a high level local vibration of steering wheel could not be avoided. As the results, the vibration source and path mechanisms are experimentally identified and then an improvement design is proposed to minimize the steering wheel vibration.

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VLSI의 논리설계 자동화를 위한 SDL 하드웨어 컴파일러 (A SDL Hardware Compiler for VLSI Logic Design Automation)

  • 조중휘;정정화
    • 대한전자공학회논문지
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    • 제23권3호
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    • pp.327-339
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    • 1986
  • In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

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DEVELOPMENT OF GEOLOGICAL DISPOSAL SYSTEMS FOR SPENT FUELS AND HIGH-LEVEL RADIOACTIVE WASTES IN KOREA

  • Choi, Heui-Joo;Lee, Jong Youl;Choi, Jongwon
    • Nuclear Engineering and Technology
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    • 제45권1호
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    • pp.29-40
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    • 2013
  • Two different kinds of nuclear power plants produce a substantial amount of spent fuel annually in Korea. According to the current projection, it is expected that around 60,000 MtU of spent fuel will be produced from 36 PWR and APR reactors and 4 CANDU reactors by the end of 2089. In 2006, KAERI proposed a conceptual design of a geological disposal system (called KRS, Korean Reference disposal System for spent fuel) for PWR and CANDU spent fuel, as a product of a 4-year research project from 2003 to 2006. The major result of the research was that it was feasible to construct a direct disposal system for 20,000 MtU of PWR spent fuels and 16,000 MtU of CANDU spent fuel in the Korean peninsula. Recently, KAERI and MEST launched a project to develop an advanced fuel cycle based on the pyroprocessing of PWR spent fuel to reduce the amount of HLW and reuse the valuable fissile material in PWR spent fuel. Thus, KAERI has developed a geological disposal system for high-level waste from the pyroprocessing of PWR spent fuel since 2007. However, since no decision was made for the CANDU spent fuel, KAERI improved the disposal density of KRS by introducing several improved concepts for the disposal canister. In this paper, the geological disposal systems developed so far are briefly outlined. The amount and characteristics of spent fuel and HLW, 4 kinds of disposal canisters, the characteristics of a buffer with domestic Ca-bentonite, and the results of a thermal design of deposition holes and disposal tunnels are described. The different disposal systems are compared in terms of their disposal density.

SVM 기반 자동 품질검사 시스템에서 상관분석 기반 데이터 선정 연구 (Study on Correlation-based Feature Selection in an Automatic Quality Inspection System using Support Vector Machine (SVM))

  • 송동환;오영광;김남훈
    • 대한산업공학회지
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    • 제42권6호
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    • pp.370-376
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    • 2016
  • Manufacturing data analysis and its applications are getting a huge popularity in various industries. In spite of the fast advancement in the big data analysis technology, however, the manufacturing quality data monitored from the automated inspection system sometimes is not reliable enough due to the complex patterns of product quality. In this study, thus, we aim to define the level of trusty of an automated quality inspection system and improve the reliability of the quality inspection data. By correlation analysis and feature selection, this paper presents a method of improving the inspection accuracy and efficiency in an SVM-based automatic product quality inspection system using thermal image data in an auto part manufacturing case. The proposed method is implemented in the sealer dispensing process of the automobile manufacturing and verified by the analysis of the optimal feature selection from the quality analysis results.

재구성 가능한 193비트 타원곡선 암호연산 서버 팜의 시스템 레벨 설계 (System Level Design of a Reconfigurable Server Farm of 193-bit Elliptic Curve Crypto Engines)

  • 문상국
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 춘계학술대회
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    • pp.656-658
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    • 2013
  • 새로운 공정 기술의 발달로, 임베디드 시스템을 구성하는 하드웨어와 소프트웨어의 복잡도는 나날이 증가하고 있다. 그 결과로, 현대의 복잡한 반도체 디자인을 전통적인 HDL을 사용한 방식으로 수행한다는 일은 점점 어려워지고 있다. 본 고에서는 SystemVerilog를 기반으로 하는 새로운 시스템 수준의 설계 방식을 적용하여 실제 회로에 구현한다. 기존에 구현한 타원곡선 암호화 엔진을 재사용하여, 시스템 레벨에서 객체 지향 개념을 살려 추상화하고, 이를 이용하여 타원곡선 암호화 서버 팜을 구현한다. 전체 시스템을 하나의 통합 설계 환경에서 성공적으로 구현하여 불필요한 노력과 시간을 50%로 축소하였다. 기존 방법으로 했다면, 하드웨어 설계에 Verilog, 시뮬레이션에 C/SystemC를 사용하여 설계와 검증에 여러 단계의 시간과 노력이 필요했을 것이다.

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A Multimedia Tutorial system for Learning the French Language

  • Jho, Gook-Hyung;Jang, Jae-Hyuk;Sim, Gab-Sig
    • 한국컴퓨터정보학회논문지
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    • 제21권1호
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    • pp.191-198
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    • 2016
  • This paper aims to present how to design and implement a multimedia tutorial system for the self-learning French language using Director with additional tools. To implement a multimedia tutorial system we need to design several steps. First, we should choose the level of the users and design tutorial. Second, we should prepare all materials such as sounds, graphics, text and video. Finally, we should implement the selected elements and control the educational software. Due to the nature of the paper, it must emphasize French basic conversation to make environment that be used in each scene and the scene of the context dialog. In view of the fact that the fitness of each content utilization field of multimedia authoring tool is high, it is possible as part of the system sizing process of the manufacturing process, to impart its meaning. This learning-contents are composed of 10 units each situation, and we anticipate there are the several effects of this system on basic French students. This system helps lecturer get French students interested in lessons, and enables learner to learn French of the role of iterative practice by linking image and sound. Also this system helps learners to prepare and review French studying after a lesson and allows leaners to maximize their efficiency. The future of this work is to implement this system on the app.

이종 곱셈 연산기 서버 팜의 시스템 레벨 설계 (A System Level Design of Heterogeneous Multiplication Server Farms)

  • 문상국
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2014년도 춘계학술대회
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    • pp.768-770
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    • 2014
  • 반도체 제조공정의 발전으로 새로운 기술에 대한 수요가 증가하여 임베디드 시스템을 구성하는 하드웨어와 소프트웨어의 설계 복잡도는 나날이 증가하고 있다. 그 결과 전통적인 설계방식으로는 현대 사회가 요구하는 복잡한 정보기기를 설계하기에 한계에 다다랐다. 본 논문에서는 SystemVerilog의 한 종류를 사용하여 맨-파워를 획기적으로 줄이면서 복잡한 하드웨어를 설계하는 새로운 방식을 소개한다. 새로운 설계방식에서는 객체 지향 구현을 바탕으로 하며, 이를 적용하여 기존의 이종 곱셈기 IP를 기본 블록으로 하는 복잡한 이종 곱셈기 서버 팜을 구현하였다. 설계는 단일 환경에서 하드웨어에서 테스트 벤치까지 구현하였다. 새로운 방식을 도입하지 않는다면 본 논문에서 소개하는 이종 곱셈연산기 서버 팜을 구현하는데 HDL 시뮬레이션, C/SystemC 검증에 많은 시간과 맨-파워가 투자되어야 할 것이다.

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피드포워드 제어를 이용한 위상차 보정 속도리플 제어기의 설계 (Design of Velocity Ripple Controller using Phase Compensation Feedforward Control)

  • 태원형;김정한;심종엽;오정석;송준엽
    • 한국정밀공학회지
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    • 제31권8호
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    • pp.705-713
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    • 2014
  • In this paper, we propose a novel velocity ripple controller using phase compensation feedforward control. Velocity ripples result in many kinds of performance degradations in manufacturing machines, especially such as ultra-precision roll lathes. The generation of velocity ripple in constant velocity control comes from various causes, such as electrical torque ripples, mechanical worn out, inconsistent mass center, etc. Conventional researches about ripple is mainly for reducing torque ripple in actuator level, which is only one of reasons for velocity ripples, so in this study, we focus on eliminating velocity ripples in upper level controller using phase compensation feedforward controller. The proposed algorithm is composed of several modules, such as ripple extractor, phase adjuster and phase follower etc. The suggested algorithm can be easily extended, and it shows a superior performance in the experiments of ultra-precision roll lathes.

NPC 멀티레벨 인버터의 고조파 분석 및 출력 필터 설계 (Harmonic Analysis and Output Filter Design of NPC Multi-Level Inverters)

  • 김윤호;방상석;김광섭;김수홍
    • 전력전자학회논문지
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    • 제11권2호
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    • pp.135-141
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    • 2006
  • 본 논문은 단상 멀티레벨 인버터의 LC출력 필터 설계와 변조비에 따른 고조파 분석을 수행하였다. 일반적으로 고전력 응용에 적합한 멀티레벨 인버터는 낮은 스위칭 주파수하에서 구동되므로 출력단에 큰 고조파 성분을 포함하게 된다. 이를 감소시키기 위해 출력단에 필터를 삽입하는 방법이 효과적이다. 3레벨 NPC 멀티레벨 인버터의 출력단 고조파를 감소시키기 위한 필터 설계 방안을 검토하고, 디지털 제어 방식을 위해 DSP(TMS320C31)를 사용하였다. 또한 필터의 설계예시를 보였고, 설계된 시스템의 타당성을 시뮬레이션과 실험을 통해 입증하였다.