• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.160-162
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• 2002

본 논문은 LCD구동 IC 패키지 제조 분야에서 사용되는 TAB IC블랭킹 금형에 대해 신속하고 합리적인 설계를 수행하기 위하여 금형설계와 관련된 다년간 축적된 경험적지식과 설계지식을 전산정보화하여 지식베이스를 구축하였고, 설계에 필요한 TAP IC 패키지의 형상정보를 제공받기 위하여 표준적인 특징형상 입력모듈을 제안하였다. 또한 지식베이스를 통해 산출된 설계 결과를 3차원 모델러와 연계하여 3차원 형상생성 및 가공도면의 자동화를 실현하여, 기존의 TAB If 블랭킹 금형설계자 뿐만 아니라 신입설계자도 바로 실무에 적용할 수 있는 시스템으로 발전시키고자 한다.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.107-110
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• 2002

Soft masks mean that part or all of the program code for operating system or applications are located in the EEPROM or flash ROM. Since Soft masks allow errors to be corrected and programs to be modified quickly and at minimal cost, they are used primarily during testing and in the field trials. This paper introduces a hardware architecture of IC card for soft masks. We suggest a new down loading scheme for soft-mask ROM connected by an I/O interface. This scheme saves the new IC card development cost and time.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1275-1282
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• 2012

This paper proposes the 16-channel LED Driver IC for Full color LED display system. The proposed LED driver IC in this paper can draw current independent of temperature and supply voltage in each channel. Current flow in the channel is configurable via an external resistor. LED brightness is adjusted by 12-Bit PWM(Pulse Width Modulation) and 8-Bit DC(Dot Correction). A real-time monitoring of IC temperature ($130^{\circ}C/150^{\circ}C$) and LED status (open/short) is provided by LED driver IC and the user can receive warning and get information on problems. A 16-channel LED driver IC is produced using 0.35 um BCD process and the size is $2.5mm{\times}2.5mm$. In this paper, channel current characteristic and channel current control function were measured in order to verify am embodied 16-channel LED driver IC by producing a single IC test board.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.60-66
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• 2000

This paper proposes a design of phone card IC with the self-test features and the hardware and software security functions. We design and verify the proposed functions with modeling the terminal system environment. The proposed phone card IC provides instructions and a non-volatile memory block containing the manufacturer / issuer / user information, the unit (money) value, and the security key. The self-test functions are designed to improve the test time degradation due to a serial I/O communication. Also some security features are implemented using hardware and software approaches.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2489-2491
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• 2003

In this study, we implement the laser pattern controller using function generator IC. Overall system consists of : (1) laser excitation circuit and laser tube, (2) two small mirrors to reflect laser beam on the screen, (3) two small motors for X, Y axis enabling each attached mirrors to rotate, (4) controller for motor control and user interface, (5) system power. We explain the architecture of the system and required theory to implement the system. Finally, experimental results are illustrated to show the performance of the system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.149-158
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• 1987

This paper describes the SEAS which is a 2-dimensional graphic editor for schematic circuit and IC mask layout. This system runs on general purpose computer and Tektronix 4110 series graphic terminal. With this system, user can edit schematic circuits and/or IC mask layout with 2 level hierarchy. This system supports more than 20 kinds of built-in symbol, user definable internal symbols, 60 macros, 16 function keys, 4 level on-screen menu operation and edit-in-place of cell in main drawing. And it provides editing functions such as reflection, rotation, move and copy of one or a group of elements, and modification of polygona geometry etc. To improve the excution speed, we used local memory of graphic terminal. For the portability of the program, the system is written in FORTRAN 77 programming language.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.500-505
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• 1997

Experimental amorphous photodiode is fabricated on CMOS IC using a-Si:H p-i-n structure. Amorphous photodiode is scuccessfully integrated on CMOS IC using amorphous Si produced by PECVD system. The PECVD system can deposit a-Si:H at low temperature so that photodiode can be integrated with CMOS IC structure without any process incompatibility. The fabricated amorphous photodiode has a breakdown voltage of below -20 V, a leakage current of about 1 $\mu\textrm{A}$, and turn-on voltage of 0.6~0.8 V. It is demonstrated that the photocurrent of optical signal can be turned on and off by a small voltage and the fabricated amorphous p-i-n photodiode can be used as an optical switch.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.702-708
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• 2020

Recently, as LED display systems have become larger, research on effective power control methods for the systems has been in progress. This paper proposes a power control method to minimize power loss due to the difference in LED characteristics for each channel of a backlight unit (BLU) system. The proposed LED driver IC has a power optimization function and detects the minimum headroom voltage for constant current operation of all channels and linearly controls the DC-DC converter output. Thus, it minimizes power consumption due to unnecessary additional voltage. In addition, it does not require a voltage sensing comparator or a voltage generation circuit for each channel. This has a great advantage in reducing the chip size and for stabilization when implementing an integrated circuit. In order to verify the proposed function, an IC was designed using Cadence and Synopsys' design tools, and it was fabricated with a Magnachip 0.35um 5V/40V CMOS process. The experiments confirmed that the proposed power control method controls the minimum required voltage of the BLU system.