• 한국정보통신학회논문지
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• 제10권6호
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• pp.1045-1054
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• 2006

본 논문에서는 MIL-STD-1553 data bus 네트워크의 다중화를 위한 버스 인터페이스 모듈의 설계에 관하여 기술하였다. 일반적으로 MIL-STD-1553 네트워크는 단일 레벨의 버스 토플로지를 사용하지만 응용 시스템의 구조에 따라 데이터 버스의 다중화가 요구된다. 버스의 다중화를 위해서는 마이크로 프로세서가 사용되며, 시스템의 하드웨어와 소프트웨어의 추가 기능이 요구된다. 설계된 인터페이스 모듈은 마이크로 프로세서의 사용 없이 통신용 트랜시버와 간단한 전자회로로 구성되어 있다. 하드웨어 테스트 및 소프트웨어 시뮬레이션 통하여 설계 제작된 모듈의 성능을 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.311-315
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• 1998

Load Flow calculation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning, operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to solve load flow equation and to modify above defects. And it preserve certain part of Jacobian matrix to shorten the time of calculation. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical result and the number of iteration got by Newton-Raphson method. The effect of time reduction showed about 28%, 30%, at each case of 39 bus, 118 bus system.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2008년도 제7회 추계학술대회 및 정기총회
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• pp.500-507
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• 2008

• 한국인터넷방송통신학회논문지
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• 제22권1호
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• pp.51-58
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• 2022

본 논문은 시각장애인의 대중교통, 특히 버스 이용을 보조하기 위한 새로운 방법을 제안한다. 시각장애인의 대다수는 버스 이용에 어려움을 겪는데, 기존의 안내시스템과 점자 블록은 큰 도움을 주지 못하는 것으로 드러났다(2017, 장애인실태조사). 본 논문에서는 시각장애인의 버스 접근성과 이동성 향상을 위해, 다음과 같은 세 가지 기능을 갖춘 시스템을 개발한다: (1)스마트 폰 애플리케이션을 이용한 승차 예약 기능, (2)버스 도착 알림 기능, (3)Beacon을 이용한 무선 하차 벨 기능. 데모환경을 구축한 후 진행한 다양한 실험을 통하여 버스 예약, 탑승, 하차가 원활히 이루어질 수 있음을 확인하였다.

• 전기의세계
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• 제21권4호
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• pp.39-44
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• 1972

This paper describes a new approach for minimizing working memory spaces without loosing too much amount of computing time in the analysis of power system faults. This approach requires the decomposition of alrge power system into several small groups of subsystems, forms individual bus impedance matrics, store them in the auxiliary memory, later assembles them to the original total system by algorithms. And also the approach uses techniques for diagonalizing primitive impedances and expanding the system bus impedance matrices by adding a fault bus. These scheme ensures a remarkable savings of working storage and continous computations of fault currents and voltages with the voried fault locations.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 융합신호처리학회논문지
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• 제6권1호
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• pp.1-7
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• 2005

본 논문은 컴퓨터 비전 기반의 인식 기법으로 주간 시내도로에 정차된 버스와 보도 사이로 접근하는 측후방 차량을 탐지하는 시스템을 설명한다. 이 시스템은 승객의 안전한 하차를 위해 버스 운전자와 승객에게 차량의 접근 유무를 알려준다. 버스의 측후방 영상은 버스가 정차할 때마다 버스 중앙 출입문 상단에 장착된 카메라에서 입력된다. 이 영상에서 버스와 보도 사이에 탐색영역을 설정하고 이 영역에서 영상의 변화와 소벨 필터링으로 차량을 탐지한다. 탐지된 차량의 중심점을 잡은 후, 위치 및 가로 세로의 크기를 이용하여 거리, 속도, 방향을 알아낸다. 이 정보를 이용하여 하차하는 승객에게 위험한 상황이라 판단될 경우, 운전자와 승객에게 위험을 알려준다. 실험결과로 시내 주행시 87% 이상의 탐지율을 나타내었다.

• 대한전기학회논문지:전력기술부문A
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• 제54권5호
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• pp.226-233
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• 2005

As the power demand has been increasing, a fault current problem is becoming more serious in real power system. Various ways like bus-split operation, transmission line open operation, are used in Korean power system for solving the problem. In this time, superconducting FCL(Fault Current Limiter) has been developed as a vary attractive alternative since HTS(High Temperature Superconductivity) was discovered. Korea, a project developing superconducting FCL to apply to 154kV transmission system is proceeding. Therefore, a power system analysis for SFCL application to power system is necessary, This paper presents the determination of quenching resistance and the selection of optimal cites when 154kV HTS-FCL is applied to Korean power system.

• 대한전기학회논문지:전력기술부문A
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• 제48권9호
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• pp.1081-1087
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• 1999

Load Flow calulation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning. operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to slove load flow equation and to modify above defects. And it preserve P-Q bus part of Jacobian matrix to shorten computing time. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical results and the same numbers of iteration obtained by Newton-Raphson method. The effect of computing time reduction showed about 28% , 30% , at each case of 39 bus, 118 bus system.

• Transactions on Electrical and Electronic Materials
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• 제17권1호
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• pp.1-6
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• 2016

Ensuring the secure operation of power systems has become an important and critical matter during the present time, along with the development of large, complex and load-increasing systems. Security constraints such as the thermal limits of transmission lines and bus-voltage limits must be satisfied under all of a system’s operational conditions. An alternative solution to improve the security of a power system is the employment of Flexible Alternating-Current Transmission Systems (FACTS). FACTS devices can reduce the flows of heavily loaded lines, maintain the bus voltages at desired levels, and improve the stability of a power network. The Unified Power Flow Controller (UPFC) is a versatile FACTS device that can independently or simultaneously control the active power, the reactive power and the bus voltage; however, to achieve such functionality, it is very important to determine the optimal location of the UPFC device, with the appropriate parameter setting, in the power system. In this paper, a genetic algorithm (GA) method is applied to determine the optimal location of the UPFC device in a network for the enhancement of the power-system loadability and the minimization of the active power loss in the transmission line. To verify our approach, simulations were performed on the IEEE 14 Bus, 30 Bus, and 57 Bus test systems. The proposed work was implemented in the MATLAB platform.