• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1449-1461
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• 2019

Face sketch synthesis plays an important role in public security and digital entertainment. In this paper, we present a novel face sketch synthesis method via local similarity and nonlocal similarity regularization terms. The local similarity can overcome the technological bottlenecks of the patch representation scheme in traditional learning-based methods. It improves the quality of synthesized sketches by penalizing the dissimilar training patches (thus have very small weights or are discarded). In addition, taking the redundancy of image patches into account, a global nonlocal similarity regularization is employed to restrain the generation of the noise and maintain primitive facial features during the synthesized process. More robust synthesized results can be obtained. Extensive experiments on the public databases validate the generality, effectiveness, and robustness of the proposed algorithm.

• Journal of Korea Multimedia Society
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• v.11 no.12
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• pp.1739-1748
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• 2008

When we conduct a data mining procedure on sample data sources, several rules are generated. But some rules are redundant or logically disjoint and therefore they can be removed. We suggest a new rule minimization algorithm inspired from logic synthesis to improve comprehensibility and eliminate redundant rules. The method can merge several relevant rules into one based on data mining and logic synthesis without high loss of accuracy. In case of two or more rules are candidates to be merged, we merge the rules with the attribute having the lowest information gain. To show the proposed method could be a reasonable solution, we applied the proposed approach to a problem domain constructing user preferred ontology in anti-spam systems.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.13-17
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• 1993

In this paper, a design method of controller which incorporates pole restriction into implicit self tuning algorithm is proposed. The idea behind pole restriction is that the closed loop poles of the system are restricted to a user-chosen circle in the region to meet maximum percentage overshoot and settling time specification. Most algorithm based on pole restriction are explicit schemes involving a parameter estimation and synthesis stage to obtain controller parameters. The object of this paper is to have an algorithm that has the idea of pole restriction and the simplicity of the implicit approach.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.81-89
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• 1996

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.75-78
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• 2000

This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp［1］high-level synthesis system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Current Optics and Photonics
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• v.5 no.6
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• pp.672-679
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• 2021

We propose a high-speed layer-based algorithm for synthesizing computer-generated holograms (CGHs), featuring sparsity-based image segmentation and computational parallelism. The sparsity-based image segmentation of layer-based three-dimensional scenes leads to considerable improvement in the efficiency of CGH computation. The efficiency enhancement of the proposed algorithm is ascribed to the field localization of the fast Fourier transform (FFT), and the consequent reduction of FFT computational complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.874-882
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• 2004

MPEG Audio compression algorithm is the international standard for the digital compression of high quality audio using mechanism of the perceptual coding based on psychoacoustic masking. It is necessary to discuss the constraints on designing of common filter banks for MPEG-2 BC and MPEG-2 AAC decoder system, which is not Down yet, mapping audio signals from the time domain into the frequency domain. In this paper, we present an architecture of common synthesis filter whcih can be used for MPEG-2 BC and MPEG-2 AAC decoder using recursive structure. The proposed algorithm is based on recursive architecture that effectively performs common compulsion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1818-1827
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• 2004

This paper carried out numerical calculation about the directivity synthesis problem in two dimension of adaptive ultrasonic transducers. Adaptive system for directivity synthesis is constructed by multi-electrode array on the surface of only one piezoelectric ceramic plate combined with optimal algorithm. In order to realize the desired directivity that is established arbitrarily, the optimal vibrational displacement is calculated by optimal algorithm (DFP method). Secondly, the optimal voltage of electrodes which is correspond to the calculated vibrational displacement is calculated used by finite element method and DFP method. And, the vibration analysis in two dimension of piezoelectric transducer carried out by means of finite element method.