• 전력전자학회논문지
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• 제10권5호
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• pp.508-517
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• 2005

본 논문은 LC 필터를 갖는 3상 인버터에 적합한 고성능 전압제어기에 대해서 기술한다. 불평형 부하 및 비선형 부하시 3상 인버터의 출력전압 왜곡을 동시에 보상 할 수 있는 새로운 동기좌표계 전압제어기를 제안한다. 제안된 제어기는 전용의 디지털 필터를 사용하여 불평형 및 비선형 부하 상태하에서도 동기좌표계의 PI 전압제어기가 3상 평형의 선형부하에서와 같이 직류값을 가지고 동작하게 함으로써 비록 전압제어기의 대역폭이 높지 않아도 정상상태 오차를 현격히 감소시킨다. 제안한 제어기의 성능의 타당성을 입증하기 위해서 모의실험 결과를 보였으며 실험을 통하여 모의실험 결과를 확인하였다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.1951-1958
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• 2009

This paper presents a synchronous-rotating-frame-based control of single-phase UPQC(Unified Power Quality Conditioner) to improve power quality in ac electrified railway systems. The simulation results show that the UPQC can compensate the harmonic supply voltages, the harmonic load currents, and the reactive power in electrified railway systems. Validity of the proposed UPQC control method based on the synchronous rotating frame is illustrated through the simulation results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.103-105
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• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.312-317
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• 1996

This paper compares the output voltage control strategies of three-phase PWM inverter for uninterruptible power supply. The feedforward control, feedforward/feedback control, and decoupled feedback control in both the synchronous reference frame and the stationary reference frame are examined. In particular, it is shown that the response of the decoupled feedback controller in the synchronous reference frame can be improved by pole-zero cancellation method. It is also shown that the pole-zero cancellation method reduces to the deadbeat control, when it is implemented with digital controller.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권2호
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• pp.107-115
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• 2006

In this paper, a new speed sensorless control based on an instantaneous reactive power is proposed for the interior permanent magnet synchronous motor(IPMSM) drives. In proposed algorithm, the current observer estimates the line currents and the estimated speed can be yielded from the voltage equation because the information of speed is included in back EMF. To implement speed sensorless control, the current observer is composed by using the voltage equation of the IPMSM in the stationary reference frame fixed to the stator. The estimated speed of the rotor is composed by using the voltage equation of the IPMSM in the rotating reference frame fixed to the rotor The estimated speeds to minimize the speed error compensated by using the instantaneous reactive power. The instantaneous reactive power is calculated on the rotating reference frame fixed to the rotor. The effectiveness of the preposed algorithm is confirmed by the experiments.

• 전력전자학회논문지
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• 제21권2호
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• pp.168-174
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• 2016

In this paper, current control using PI controller in the synchronous reference frame is analyzed through the relationship among bandwidth, resonance frequency, and sampling frequency in the grid-connected inverter with LCL filter. Stability is investigated by using bode plot in frequency domain and root locus in discrete domain. The feedback variable is the grid current, which is regulated by the PI controller in the synchronous reference frame. System delay is modeled as 1.5Ts, which contains computational and PWM modulator delay. Two resonance frequencies are given at 815 Hz and 3.16 kHz from LCL filter parameters. Sufficient phase and gain margins can be obtained to guarantee stable current control, in case that resonance frequency is above one-sixth of the sampling frequency. Unstable current control is performed when resonance frequency is below one-sixth of the sampling frequency. Analysis results of stability from frequency response and discrete response is the same regardless of resonance frequency. Finally, stability of current control based on theoretical analysis is clearly verified through simulation and experiment in grid-connected inverters with LCL filter.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.458-460
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• 1996

In this study, the full-state flux observer is designed in the synchronous DQ-frame and the speed adaptation rule is derived by using the MRAS(Model Reference Adaptive System) theory. In this rule, the induction motor becomes a reference model and the flux observer is taken as a adjustable model. A guideline of the adaptation gain is investigated for the precise and stable speed adaptation and the proposed scheme is compared with the conventional one designed in the stationary DQ-frame.

• Journal of Power Electronics
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• 제16권1호
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.

• 전자공학회논문지S
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• 제34S권12호
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• pp.10-18
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• 1997

The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.