• Title/Summary/Keyword: Synchronous Data Flow

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Efficient Construction of Over-approximated CFG on Esterel (Esterel에서 근사-제어 흐름그래프의 효율적인 생성)

  • Kim, Chul-Joo;Yun, Jeong-Han;Seo, Sun-Ae;Choe, Kwang-Moo;Han, Tai-Sook
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.11
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    • pp.876-880
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    • 2009
  • A control flow graph(CFG) is an essential data structure for program analyses based on graph theory or control-/data- flow analyses. Esterel is an imperative synchronous language and its synchronous parallelism makes it difficult to construct a CFG of an Esterel program. In this work, we present a method to construct over-approximated CFGs for Esterel. Our method is very intuitive and generated CFGs include not only exposed paths but also invisible ones. Though the CFGs may contain some inexecutable paths due to complex combinations of parallelism and exception handling, they are very useful for other program analyses.

Discrete-Time Queuing Analysis of Dual-Plane ATM Switch with Synchronous Connection Control

  • Choi, Jun-Kyun
    • ETRI Journal
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    • v.19 no.4
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    • pp.326-343
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    • 1997
  • In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane $16{\times}16$ switch would have the acceptable performance with maximum throughput of about 95 percent.

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Performance of MAC frame Fragmentation and Efficient Flow Control Schemes for Synchronous Ethernet Systems (동기식 이더넷 시스템용 MAC 프레임 분할 방식과 효율적인 흐름제어 방식의 성능 분석)

  • Choi Hee-Kyoung;Yoon Chong-Ho;Cho Jae-Hun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.12B
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    • pp.838-846
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    • 2005
  • In this paper, we consider the following two issues for implementing the synchronous Ethernet systems. First, a synchronous Ethernet system employs a fixed size superframe which is divided into a synchronous period and an asynchronous one. We note that the starting point of a superframe is not deterministic when an ordinary data frame's transmission is overlapped the superframe boundary. This overlap may be a fatal drawback for strict jitter bounded applications. Circumventing the problem, we propose a frame fragmentation scheme to provide a zero jitter, and compare its delay performance with the hold scheme which also provides the zero jitter. We next concern that IEEE 802.3x pause frames cannot be promptly transmitted in a synchronous period, and thus asynchronous traffics may be dramatically get dropped at the input buffer of a switch. To handle the problem, we propose an efficient flow control by allowing the transmission of the pause frame in a synchronous period, and investigate the blocking probability of the asynchronous traffics by the simulation.

Specification, verification, and implementation of an embedded system with SCADE/Lustre (SCADE/Lustre를 이용한 임베디드 시스템의 명세, 검증 및 구현)

  • Song, Gwan-Ho;Sim, Jae-Hwan;Ahn, Young-Jung;Choi, Jin-Young
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.10a
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    • pp.443-448
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    • 2006
  • 본 논문은 safety critical 실시간 반응형 시스템 하에서의 임베디드 소프트웨어 개발에 적합한 방법을 찾기 위해서 여러 가지 정형기법에 대해 논의하고 그 중 하나인 SCADE를 이용해 실제 임베디드 시스템을 직접 명세하고 검증한 후 구현한 내용을 서술한다. 본 논문에서는 data flow synchronous 언어인 Lustre를 소개하고, 소개된 언어가 실시간 반응형 시스템의 검증과 구현에 왜 적합한지를 논의하며, 하나의 시스템을 SCADE를 이용해서 명세하고 검증한 후 구현 한다. 수행된 실험을 통해서 data flow synchronous 언어는 실시간 반응형 시스템의 명세, 구현 그리고 검증에 적합한 언어라는 것을 언급하고, 이 언어의 사용이 복잡한 임베디드 시스템 개발에 효과적으로 사용될 수 있음을 제시한다.

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An optimization of synchronous pipeline design for IP-based H.264 decoder design (IP기반 H.264 디코더 설계를 위한 동기화 파이프라인 최적화)

  • Ko, Byung-Soo;Kong, Jin-Hyeung
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.407-408
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    • 2008
  • This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.

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A GPU scheduling framework for applications based on dataflow specification (데이터 플로우 기반 응용들을 위한 GPU 스케줄링 프레임워크)

  • Lee, Yongbin;Kim, Sungchan
    • Journal of Korea Multimedia Society
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    • v.17 no.10
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    • pp.1189-1197
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    • 2014
  • Recently, general purpose graphic processing units(GPUs) are being widely used in mobile embedded systems such as smart phone and tablet PCs. Because of architectural limitations of mobile GPGPUs, only a single program is allowed to occupy a GPU at a time in a non-preemptive way. As a result, it is difficult to meet performance requirements of applications such as frame rate or response time if applications running on a GPU are not scheduled properly. To tackle this difficulty, we propose to specify applications using synchronous data flow model of computation such that applications are formed with edges and nodes. Then nodes of applications are scheduled onto a GPU unlike conventional scheduling an application as a whole. This approach allows applications to share a GPU at a finer granularity, node (or task)-level, providing several benefits such as eliminating need for manually partitioning applications and better GPU utilization. Furthermore, any scheduling policy can be applied in response to the characteristics of applications.

An Optimal ILP Scheduling Algorithm on Linear Data-Flow Graph for Multiprocessor Design (멀티프로세서 설계를 위한 Linear Data-Row Graph의 최적화 ILP 알고리즘)

  • Kim Ki-Bog;Lin Chi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.6 s.336
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    • pp.49-58
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    • 2005
  • In this paper, we propose an optimal ILP scheduling algorithm for multiprocessor design on LDFG(Linear Data-Flow Graph) that can be represented by homogeneous synchronous data-flow. The proposed computation in this paper does not contain data-dependent, all scheduling decisions for such algorithms can be taken at compile time, only fully static overlapped schedules are considered. It means that all linear have the same schedule and the same processor assignment. In this paper, the resource-constrained problem is addressed, for the LDFG optimization for multiprocessor design problem formulating ILP solution available to provide optimal solution. The results show that the scheduling method is able to find good quality schedules in reasonable time.

Implementation Of Moving Picture Transfer System Using Bluetooth (Bluetooth를 이용한 동영상 전송 시스템 구현)

  • 조경연;이승은;최종찬
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.25-28
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    • 2001
  • In this paper we implement moving picture transfer system using bluetooth Development Kit (DK). To reduce the size of the image data, we use M-JPEG compression. We use bluetooth Synchronous Connection-Oriented (SCO) link to transfer voice data. Server receive image data from camera and compress the image data in M-JPEG format, and then transmit the image data to client using bluetooth Asynchronous connection-less (ACL) link. Client receive image data from bluetooth ACL link and decode the compressed image and then display the image to screen. Sever and Client can transmit and receive voice data simultaneously using bluetooth SCO link. In this paper bluetooth HCI commands and events generated by host controller to return the results of HCI commands are explained and the flow of bluetooth connection procedure is presented.

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Development of UPFC GTO Thyristor Valve Test Equipment (UPFC GTO Thyristor VTE(Valve Test Equipment) 개발)

  • Kim, Soo-Yeol;Chang, Byung-Hoon;Yoon, Jong-Soo;Kim, Yong-Hak;Baek, Doo-Hyun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.13 no.5
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    • pp.391-395
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    • 2008
  • KEPCO 80MVA UPFC has been operated in Gangjin Substation since May 2003. This UPFC is composed of 40MVA shunt inverter and 40MVA series inverter, and developed in technical cooperation between Hyosung and Siemens. KEPCO has tried to localize UPFC control technique after its installation and developed GTO Thyristor Valve Test Equipment for annual maintenance test. The development of this equipment make it possible to process GTO Thyristor module test automatically and manage historic data systematically, which could improve UPFC reliability.

Development of Cooperated Control System for Multiple FACTS in KEPCO Power Systems (다기의 FACTS 기기 협조제어 시스템 개발)

  • Chang, Byung-Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.10
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    • pp.1726-1730
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    • 2008
  • In this paper, the application schemes for coordinated control system of multiple FACTS were presented to enhance the voltage stability around the metropolitan areas. In order to coordinated control of FACTS devices, f-V analysis method which is one of the indices for voltage stability was performed with real time network data which is transferred from SCADA/EMS system. If the system is unstable after contingencies, the new operation set-point of FACTS would be determined using bus sensitivity from tangent vector at voltage instability point. Otherwise, we would determine the new operation set-point of FACTS for considering economical operation, like as active power loss minimization using Optimal Power Flow algorithm. In simulation, the SCADA/EMS 2007's data are used for studying the coordinated control algorithm of multiple FACTS devices that is installed or will be installed in KOREA power system