• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.117-122
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• 2021

Permanent magnet synchronous motors can secure high power density and efficiency, but have problems in that the materials required for manufacturing are expensive and design is somewhat more difficult than induction motors. Therefore, it is necessary to develop an optimal motor that considers both efficiency and maintenance convenience and related control research. In addition, driving by a practical motor leads to a request to increase the highest efficiency in a narrow rated range, an increase in average efficiency in the entire electric driving range, and an increase in average output. Due to this movement, a reluctance motor that does not require a permanent magnet is being considered as an alternative. In this paper, in line with the issues of the times that require the development of future technology that can replace rare earth permanent magnet motors and the technological preemption of rare earth reduction motors and rare earth motors, switched reluctance motors without permanent magnet For motor, SRM), modeling through machine language (C language) and the characteristics of SRM accordingly are to be studied.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1596-1602
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• 2021

Battery-operated IoT devices in IoT systems require low power consumption. In general, IoT devices enter a sleep state synchronously to reduce power consumption. A problem arises when an IoT device has to handle asynchronous user requests, as the duty cycle must be reduced to enhance response time. In this paper, we propose a new low-power-consumption scheme, called Repetitive Wake-up scheme for IoT systems of asynchronous environments such as indoor lights control. The proposed scheme can reduce power consumption by sending wake-up signals from the smartphone repetitively and by retaining the IoT device in sleep state to the smallest possible duty cycle. In the various environments with IoT devices at home or office space, we showed that the proposed scheme can reduce power consumption by up to five times compared to the existing synchronous interlocking technique.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.3
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• pp.423-431
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• 2022

The UPS(Uninterruptible Power Supply) system operates in the battery charging mode when the grid is normal, and in the UPS mode, which is the battery discharge mode when a grid error occurs. Since the UPS must supply the same voltage as the grid to the load within 4 [ms] in case of a grid error, the switching time and power recovery time should be short when controlling the output voltage and current of the UPS, and the power failure detection time is also important. The power outage detection algorithm using DFT(Discrete Fourier Transform) proposed in this paper compares the grid voltage waveform with the voltage waveform including the 9th harmonic generated through DFT using Schmitt trigger to detect power outage faster than the existing power outage monitoring algorithm. There are advantages. Therefore, it is possible to supply instant and stable power when switching modes in the UPS system. The multi-power-applied UPS system proposed in this paper uses DFT, which is faster than the conventional blackout monitoring algorithm in detecting power failure, to provide stable power to the load in a shorter time than the existing power outage monitoring algorithm when a system error occurs. The detection method was applied. The changeover time of mode switching was set to less than 4 [ms], which is 1/4 of the system cycle, in accordance with KSC 4310 regulation, which was established by the Industrial Standards Council on the regulation of uninterruptible power supply. A 10 [kW] UPS system in which commercial voltage, vehicle generator, and auxiliary diesel generator can be connected to each of the proposed transfer devices was constructed and the feasibility was verified by conducting an experiment.

• Journal of IKEEE
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• v.26 no.1
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• pp.95-103
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• 2022

In this paper, the efficiency of a sensorless method with square-wave injection for a low-cost inverter, so called B4 inverter is presented. This inverter comprises only 4 switches to reduce system cost. It is distinguished from the conventional B6 inverter that has 6 of switching elements. The B4 inverter, injected a 1 kHz of harmonic wave, has been modelled using the functions and library in Matlab/Simulink. This paper described each component of sensorless algorithm. Among them, the Notch Filter is used to extract the harmonic component of the phase current and a second-order low-pass filter was used to reduce the ripple of the estimated speed. It is shown through simulation that the rotor angle of a permanent magnet synchronous motor is detected by multiplying the current waveform extracted using the notch filter by the harmonic voltage. The feasibility of the proposed method is shown through Simulink simulation.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.157-168
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• 2009

In this paper, a photovoltaic system is designed with a step up chopper and single phase PWM(Pulse Width Modulation) voltage source inverter. Where proposed Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical voltage and current dropping character. The single phase PWM voltage source the inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power. from 10 to 20[%]. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In order to enhance the efficiency of photovoltaic cells, photovoltaic positioning system using sensor and microprocessor was design so that the fixed type of photovoltaic cells and photovoltaic positioning system were compared. In result, photovoltaic positioning system can improved 5% than fixed type of photovoltaic cells. In addition, I connected extra power to the system through operating the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and the phase of single-phase inverter of PWM voltage type can be synchronized. And, It controlled in order to provide stable pier to the load and the system through maintaining high lurer factor and low output power of harmonics.

• Journal of Korean Neurosurgical Society
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• v.64 no.6
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• pp.983-994
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• 2021

Objective : The effectiveness of gamma knife radiosurgery (GKR) in the treatment of brain metastases is well established. The aim of this study was to evaluate the efficacy and safety of maximizing the radiation dose in GKR and the factors influencing tumor control in cases of small and medium-sized brain metastases from non-small cell lung cancer (NSCLC). Methods : We analyzed 230 metastatic brain tumors less than 5 mL in volume in 146 patients with NSCLC who underwent GKR. The patients had no previous radiation therapy for brain metastases. The pathologies of the tumors were adenocarcinoma (n=207), squamous cell carcinoma (n=18), and others (n=5). The radiation doses were classified as 18, 20, 22, and 24 Gy, and based on the tumor volume, the tumors were categorized as follows : small-sized (less than 1 mL) and medium-sized (1-3 and 3-5 mL). The progression-free survival (PFS) of the individual 230 tumors and 146 brain metastases was evaluated after GKR depending on the pathology, Eastern Cooperative Oncology Group (ECOG) performance score (PS), tumor volume, radiation dose, and anti-cancer regimens. The radiotoxicity after GKR was also evaluated. Results : After GKR, the restricted mean PFS of individual 230 tumors at 24 months was 15.6 months (14.0-17.1). In small-sized tumors, as the dose of radiation increased, the tumor control rates tended to increase (p=0.072). In medium-sized tumors, there was no statistically difference in PFS with an increase of radiation dose (p=0.783). On univariate analyses, a statistically significant increase in PFS was associated with adenocarcinomas (p=0.001), tumors with ECOG PS 0 (p=0.005), small-sized tumors (p=0.003), radiation dose of 24 Gy (p=0.014), synchronous lesions (p=0.002), and targeted therapy (p=0.004). On multivariate analyses, an improved PFS was seen with targeted therapy (hazard ratio, 0.356; 95% confidence interval, 0.150-0.842; p=0.019). After GKR, the restricted mean PFS of brain at 24 months was 9.8 months (8.5-11.1) in 146 patients, and the pattern of recurrence was mostly distant within the brain (66.4%). The small and medium-sized tumors treated with GKR showed radiotoxicitiy in five out of 230 tumors (2.2%), which were controlled with medical treatment. Conclusion : The small-sized tumors were effectively controlled without symptomatic radiation necrosis as the radiation dose was increased up to 24 Gy. The medium-sized tumors showed potential for symptomatic radiation necrosis without signifcant tumor control rate, when greater than 18 Gy. GKR combined targeted therapy improved the tumor control of GKR-treated tumors.

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.