• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.432-434
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• 2006

The additional matters appear to be considered in several aspects for building up power-quality measuring system of transmission system(high voltage system) compared to distribution system(middle or low voltage system). Like in distribution system, input signals are also received from PT and CT source of voltage and current respectively in transmission system and applied in accordance with a certain rate. In this case, very big error rate can be occurred according to the specification of the measuring system as the applying rate is bigger than in distribution system beyond comparison. In addition, when the abnormal signal occurred such as sag/swell, interruption, transient etc., power quality of other sires linked to the system also should be checked to find the accurate cause of the abnormal power-quality signals from the corresponding. site. Accordingly, the accurate diagnosis on the condition of power quality for the system depends on the way how the synchronization system is brought along for each site. This paper will suggest the solution for the most effective system building focused on how to solve the problem of the error rate and synchronization described in the above when building up the measuring system of power quality for transmission system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.286-294
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• 2011

Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM) and extended RS coding scheme. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.

• The Journal of the Acoustical Society of Korea
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• v.38 no.1
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• pp.1-8
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• 2019

This paper estimated communication parameters according to underwater channel environment of lake for underwater acoustic communication. This paper calculated coherence time and coherence bandwidth through two experiments in actual lake environments. In both experiments, the chirp signal for channel estimation and the BPSK (Binary Phase Shift Keying) signal for calculating the bit error rate were transmitted. In each experiment, the distance between transmitter and receiver was 300 m to 400 m, and 500 m to 600 m. The coherence times calculated in experiment 1 and experiment 2 are 175 msec and 340 msec, and the coherence bandwidths are 10 Hz and 5.71 Hz, respectively. It is confirmed that the experimental results are more appropriate because the synchronization and the bit error rate performance are better only when the length of the synchronization signal and the interval of the pilot signal in the frame are shorter than the coherence time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.113-122
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• 2010

In this paper, we propose a CP (Cyclic Prefix) detection based SSS (Secondary Synchronization Signal) detection method for initial cell search in 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) FDD/TDD (Frequency Division Duplex/Time Division Duplex) dual mode downlink receiver. In general, a blind coherent SSS detection method which can detect SSS without CP detection is applied. However, coherent detection method caused performance degradation by channel compensation error at high speed environment because it uses estimated CFR (Channel Frequency Response) at PSS (Primary Synchronization Signal), and it can be more serious problem in TDD mode due to increased distance between PSS and SSS. Also blind detectionhas the drawback of high computational complexity. Therefore, we proposed a CP type pre-decision structure with non-coherent SSS detection which has stable operation in high speed channel environments for 3GPP LTE TDD mode as well as FDD mode, and can reduce computational complexity by applying CP detection before SSS detection. Simulation results show that the proposed method has stable operation for 3GPP LTE TDD/FDD dual mode downlink receiver in various channel environments.

• Journal of Broadcast Engineering
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• v.25 no.6
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• pp.870-881
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• 2020

This paper presents cell ID (cell identity) detection schemes using PSS/SSS (primary synchronization signal/secondary synchronization signal) for 5G NR (new radio) system and evaluates the detection performance. In this paper, we consider two cell ID detection schemes, i.e. two-stage detection and joint detection schemes. The two-stage detection scheme consists of two stages which estimate a channel gain between a transmitter and receiver and detect the PSS and SSS sequences. The joint detection scheme jointly detects the PSS and SSS sequences. In addition, this paper presents coherent and non-coherent combining schemes. The coherent scheme calculates the correlation value for the total length of the given PSS and SSS sequences, and the non-coherent combining scheme calculates the correlation within each group by dividing the total length of the sequence into several groups and then combines them non-coherently. For the detection schemes considered in this paper, the detection error rates of PSS, SSS and overall cell ID are evaluated and compared through computer simulations. The simulation results show that the joint detection scheme outperforms the two-stage detection scheme for both coherent and non-coherent combining schemes, but the two-stage detection scheme can greatly reduce the computational complexity compared to the joint detection scheme. In addition, the non-coherent combining detection scheme shows better performance under the additive white Gaussian noise (AWGN), fixed, and mobile environments.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2588-2593
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• 2003

Any system has the possibility of an error occurrence. Even if trivial errors were occurred, the original system would be fatally affected by the occurring errors. Accordingly, the error detection must be demanded. In this paper, we developed a real-time error detection system would be able to apply to an electronic Jacquard system. A Jacquard is a machine, which controls warps while weaving textiles, for manufacturing patterned cloth. There are two types of mechanical and electronic Jacquard. An electronic Jacquard is better than a mechanical Jacquard in view of the productivity and realizability for weaving various cloths. Recent weaving industry is growing up increasingly due to the electronic Jacquard. But, the problem of wrong weaving from error data exists in the electronic Jacquard. In this research, a real-time error detection system for an electronic Jacquard is developed for detecting errors in an electronic Jacquard in real-time. The real-time system is constructed using PC-based embedded system architecture. The system detects the occurring errors in real-time by storing 1344 data transferred in serial from an electronic Jacquard into memory, and then by comparing synchronously 1344 data stored into memory with 1344 data in a design file before the next data would be transferred to the Jacquard for weaving. The information of detected errors are monitored to the screen and stored into a file in real-time as the outputs of the system. In this research, we solve the problem of wrong weaving through checking the weaving data and detecting the occurred errors of an electronic Jacquard in real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1024-1031
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• 1999

In order to transmit high-speed wide band signals efficiently in multipath fading environments, M-ary QAM signalling combined with OFDM transmission technique is applied. In this paper, the effect of synchronization error caused by carrier frequency offset and SER(Symbol Error Rate) performance of OFDM-16QAM and OFDM-64QAM are theoretically analyzed. Our result shows that as the number of sub-carrier in OFDM system increases the frequency-offset caused inter-channel interference(ICI) increases significantly, and that an error floor occurs even at high SNR of OFDM system. For OFDM-64QAM, the error floor occurs at SER=1$\times$10-7 when a normalized frequency-offset is 0.001, in which the SNR degradation is much greater than that of OFDM-16QAM. From this study the maximum allowable frequency-offset of OFDM-16QAM and OFDM-64QAM systems can be determined to meet the specific SER requirement.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.2
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• pp.129-137
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• 2016

To identify the cause of the error and maintain the health of system, an administrator usually analyzes event log data since it contains useful information to infer the cause of the error. However, because today's systems are huge and complex, it is almost impossible for administrators to manually analyze event log files to identify the cause of an error. In particular, as OpenStack, which is being widely used as cloud management system, operates with various service modules being linked to multiple servers, it is hard to access each node and analyze event log messages for each service module in the case of an error. For this, in this paper, we propose a novel message-based log analysis method that enables the administrator to find the cause of an error quickly. Specifically, the proposed method 1) consolidates event log data generated from system level and application service level, 2) clusters the consolidated data based on messages, and 3) analyzes interrelations among message groups in order to promptly identify the cause of a system error. This study has great significance in the following three aspects. First, the root cause of the error can be identified by collecting event logs of both system level and application service level and analyzing interrelations among the logs. Second, administrators do not need to classify messages for training since unsupervised learning of event log messages is applied. Third, using Dynamic Time Warping, an algorithm for measuring similarity of dynamic patterns over time increases accuracy of analysis on patterns generated from distributed system in which time synchronization is not exactly consistent.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.169-178
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• 2007

In this paper, we propose a signal structure and its optimum receiver to improve performance of SC-FDE(Single Carrier with Frequency Domain Equalization) system. Conventional SC-FDE systems have a drawback of power unbalance in frequency domain due to generation of pilot signals in time domain. The unbalanced power in frequency domain induces a channel estimation error and the performance of the receiver is degraded significantly. To overcome the drawback we apply CAZAC sequence which has constant power distribution in time and frequency domain. We design the signal structure to improve the performance with the repeated CAZAC sequence, and we design a receiver to optimize the proposed structure. Computer simulation results show that the proposed structure is superior to the conventional structure considering frame synchronization, frequency synchronization and channel equalization on typical wireless mobile channel environment.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.