• Title/Summary/Keyword: Synchronization constraint

Search Result 21, Processing Time 0.044 seconds

Revisting Clock Synchronization Problems : Static and Dynamic Constraint Transformations for Real Time Systems (시계 동기화 문제의 재 고찰 : 실시간 시스템을 위한 정적/동적 제약 변환 기법)

  • Yu, Min-Su;Park, Jeong-Geun;Hong, Seong-Su
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.26 no.10
    • /
    • pp.1264-1274
    • /
    • 1999
  • 본 논문에서는 분산된 클록들을 주기적으로 동기화 시키는 분산 실시간 시스템에서 시간적 제약을 만족시키기 위한 정적/동적 시간 제약(timing constraint) 변환 기법을 제안한다. 전형적인 이산클록동기화(discrete clock synchronization) 알고리즘은 클록의 값을 순간적으로 조정하여 클록의 시간이 불연속적으로 진행한다. 이러한 시간상의 불연속성은 시간적 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다.클록 시간의 불연속성을 피하기 위해 일반적으로 연속클록동기화(continuous clock synchronization) 기법이 제안되고 있지만 소프트웨어적으로 구현되면 많은 오버헤드를 유발시키는 문제점이 있다. 본 논문에서는 시간적 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였으며, 이를 통해 기존의 이산클록동기화 알고리즘을 수정하지 않고서도 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있도록 하였다. 아울러 DCT에 의해 이산클록동기화 하에서 생성된 태스크 스케쥴이 연속클록동기화에 의해 생성된 스케쥴과 동일함을 증명하여 DCT의 동작이 이론적으로 정확함을 증명하였다.또한 분산 실시간 시스템에서 지역 클록(local clock)이 기준 클록과 완벽하게 일치하지 않아서 발생하는 스케쥴링상의 문제점을 다루었다. 이를 위해 먼저 두 가지의 스케쥴링 가능성, 지역적 스케쥴링 가능성(local schedulability)과 전역적 스케쥴링 가능성(global schedulability)을 정의하고, 이를 위해 시간적 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation) 기법을 제안하였다. SCT를 통해 지역적으로 스케쥴링 가능한 태스크는 전역적으로 스케쥴링이 가능하므로, 단지 지역적 스케쥴링 가능성만을 검사하면 스케쥴링 문제를 해결할 수 있도록 하였고 이를 수학적으로 증명하였다.Abstract In this paper, we present static and dynamic constraint transformation techniques for ensuring timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. Traditional discrete clock synchronization algorithms that adjust local clocks instantaneously yield time discontinuities. Such time discontinuities lead to the loss or the gain of events, thus raising serious run-time faults.While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much run-time overhead to be implemented in software. We propose a dynamic constraint transformation (DCT) technique which can solve the problem without modifying discrete clock synchronization algorithms. We formally prove the correctness of the DCT by showing that the DCT with discrete clock synchronization generates the same task schedule as the continuous clock synchronization.We also investigate schedulability problems that arise when imperfect local clocks are used in distributed real-time systems. We first define two notions of schedulability, global schedulability and local schedulability, and then present a static constraint transformation (SCT) technique. The SCT ensures that it is sufficient to check the schedulability of a task locally in a node with a local clock, since the global schedulability of the task is derived from its local schedulability through SCT. We formally prove the correctness of SCT.

Power Consumption Analysis of Prominent Time Synchronization Protocols for Wireless Sensor Networks

  • Bae, Shi-Kyu
    • Journal of Information Processing Systems
    • /
    • v.10 no.2
    • /
    • pp.300-313
    • /
    • 2014
  • Various Time Synchronization protocols for a Wireless Sensor Network (WSN) have been developed since time synchronization is important in many time-critical WSN applications. Aside from synchronization accuracy, energy constraint should also be considered seriously for time synchronization protocols in WSNs, which typically have limited power environments. This paper performs analysis of prominent WSN time synchronization protocols in terms of power consumption and test by simulation. In the analysis and simulation tests, each protocol shows different performance in terms of power consumption. This result is helpful in choosing or developing an appropriate time synchronization protocol that meets the requirements of synchronization accuracy and power consumption (or network lifetime) for a specific WSN application.

Design and Evaluation of a Distributed Multimedia synchronization Algorithm based on the Fuzzy Logic

  • Oh, Sun-Jin;Bae, Ihn-Han
    • Proceedings of the Korean Institute of Intelligent Systems Conference
    • /
    • 1998.06a
    • /
    • pp.246-251
    • /
    • 1998
  • The basic requirement of a distributed multimedia system are intramedia synchronization which asks the strict delay and jitter for the check period of media buffer and the scaling duration with periodic continuous media such as audio and video media, and intermedia synchronization that needs the constraint for relative time relations among them when several media are presented in parallel. In this paper, a distributed multimedia synchronization algorithm based on the fuzzy logic is presented and the performance is evaluated through simulation. Intramedia synchronisation algorithm uses the media scaling techniques and intermedia synchronization algorithm uses variable service rates on the basis of fuzzy logic to solve the multimedia synchronization problem.

  • PDF

Revisiting Clock Synchronization Problems: Static and Dynamic Constraint Transformation for Correct Timing Enforcement (실시간 제약 조건의 동적/정적 변화를 통한 클록 동기화 문제 해결)

  • 유민수;홍성수
    • Proceedings of the Korean Information Science Society Conference
    • /
    • 1998.10a
    • /
    • pp.68-70
    • /
    • 1998
  • 본 논문에서는 클록들을 주기적으로 동기화하는 분산 실시간 시스템에서 주어진 태스크의 시간 제약(timing constraint)을 변환시는 구가지 기법을 제안한다. 전형적인 이산 클록 동기화(discrete clock synchronization)알고리즘은 클록의 값을 순간적으로 보정(correct)하여 클록의 시간이 불연속적으로 진행학 한다. 이러한 시간상의 불연속성은 태스크의 시작제한시간(release time)이나 종료시한(deadline)과 같은 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다. 클록 시간의 불연속성을 피하기 위해 일반적으로 연속 클록 동기화(continuous clock synchronization) 기법이제안되었지만 소프트웨어적으로 구현되기에는 많은 오버헤드를 유발시키는 문제점이 있다. 이에 따라 연속 클록 동기화는 PLL (Phase-Locked Loop)을 이용한 별도의 하드웨어를 사용하는 것이 보통이다. 본 논문에서는 연속 클록 동기화 기법을 사용하는 대신, 태스크의 시간 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였다. DCT는 소프트웨어 으로 구현이 가능하여 새로운 하드웨어를 필요로 하지 않으며, 이를 통해 기존의 이산적으로 동기화된 시스템에서 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있다. 또 다른 문제점으로서, 클록의 물리적인 특성으로 인해 동기화된 클록들이 상한된(bounded from the above)오차(skew)를 갖는다는 것이다. 이러한 오차는 지역 클록(local clock)에 대해 만족될 수 있는 임의의 실기간 제약 조건이 전역 클록(global clock)에 대해서는 만족되지 않을 수 있음을 의미한다. 본 논문에서는 이를 위해 먼저 두 가지의 스케줄링 가능성, 지역적 스케줄링 가능서(local schedulability)과 전역적 스케줄링 가능성(global schedulability)을 정의하고, 실시간 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation)기법을 제안하였다. SCT를 통해 지역적으로 스케줄링 가능한 태스크는 전역적으로 스케줄링이 가능하므로, 단지 지역적 스케줄링 가능성만을 검사하면서 스케줄링 문제를 해결할 수 있도록 하였다.

  • PDF

Design and Evaluation of a Distributed Intermedia Synchronization Algorithm based on the Fuzzy Logic

  • Oh, Sun-Jin;Bae, Ihn-Han
    • Journal of Korea Multimedia Society
    • /
    • v.1 no.1
    • /
    • pp.18-25
    • /
    • 1998
  • The basic requirements of distributed multimedia systems are intramedia synchronization which asks the strict delay and jitter for the check period of media buffer and the scaling duration with periodic continuous media such as audio and video media, and intermedia synchronization that needs the constraint for relative time relations among them when several media are presented in parallel. In this paper, a distributed intermedia synchronization algorithm that solves the intermedia synchronization problem by using variable service rates based on the fuzzy logic is designed and then the performance is evaluated through simulation.

  • PDF

Semantic Synchronization of Shared Data for Unstable Mobile Environment (불안정 모바일 네트워크 환경에서 공유 데이터 의미 동기화 기법)

  • Hong, Dong-Kweon
    • Journal of the Korean Institute of Intelligent Systems
    • /
    • v.25 no.6
    • /
    • pp.551-557
    • /
    • 2015
  • Synchronization methods for shared data need to be selected properly based on characteristics of data and applications. In this paper we suggest a new semantic synchronization method, semanticAppr, for non_transactional data in disconnected mode. Our approach reduces loss of works in cooperative environments by weakening constraint of serializability. In addition it reduces data transfer by sending operation log instead document itself.

Response Time Analysis Considering Sensing Data Synchronization in Mobile Cloud Applications (모바일 클라우드 응용에서 센싱 데이터 동기화를 고려한 응답 시간 분석)

  • Min, Hong;Heo, Junyoung
    • The Journal of the Institute of Internet, Broadcasting and Communication
    • /
    • v.15 no.3
    • /
    • pp.137-141
    • /
    • 2015
  • Mobile cloud computing uses cloud service to solve the resource constraint problem of mobile devices. Offloading means that a task executed on the mobile device commits to cloud and many studies related to the energy consumption have been researched. In this paper, we designed a response time model considering sensing data synchronization to estimate the efficiency of the offloading scheme in terms of the response time. The proposed model considers synchronization of required sensing data to improve the accuracy of response time estimation when cloud processes the task requested from a mobile device. We found that the response time is effected by new sensing data generation rate and synchronization period through simulation results.

Sequencing Constraints-based Regression Testing of Concurrent Programs After Specification Changes (명세 변경 후 병행 프로그램의 순서 제약조건 기반 회귀 테스팅)

  • Kim, Hyeon-Soo;Chung, In-Sang;Bae, Hyun-Seop;Kwon, Yong-Rae;Lee, Dong-Gil
    • Journal of KIISE:Software and Applications
    • /
    • v.27 no.4
    • /
    • pp.370-383
    • /
    • 2000
  • This paper describes a new technique known as specification-based regression testing that is used for the revalidation of concurrent programs after changes are made to specifications. This type of regression testing requires sequencing constraint that specify precedence relations on the synchronization events. In order to extract sequencing constraint automatically, we use Message Sequence Charts(MSCs) that are considered partial and nondeterministic specifications. We show how to identify which sequencing constraint is affected by the modifications made to a specification rather than creating new sequencing constraint from scratch to reduce the cost of regression testing. We also describe how to determine that each affected sequencing constraint is satisfied by a program being tested.

  • PDF

Implementation technique of execution time predictable real-time mechanism control language (실행시간 예측가능한 실시간 메카니즘 제어언어의 구현기법)

  • 백정현;원유헌
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.22 no.6
    • /
    • pp.1365-1376
    • /
    • 1997
  • In this paper, we designed real time mechanism control language and proposed execution time analysis technique. It was impossible to handle real-time mechanism control programs like programmable controller, numerical controller, distributed control system and robot controller with general purpose programming languages and operating systems because they have to process electric signals generated by thousands of sensors at the same at the same time and in real time. So we made it possible to predict plausibility of time constraint constructs of tiem constraint construct of a real time application program at compilation time by adding time constraint constructs and mechanism synchronization structure to conditional statement and iteration statement of a programming language and developing execution time analysis technique.

  • PDF

Low-power Frequency Offset Synchronization for IEEE 802.11a Using CORDIC Algorithm (CORDIC을 이용한 IEEE 802.11a용 저전력 주파수 옵셋 동기화기)

  • Jang, Young-Beom;Han, Jae-Woong;Hong, Dae-Ki
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.46 no.2
    • /
    • pp.66-72
    • /
    • 2009
  • In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.