• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.214-217
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• 2003

In this paper, we deal with implementing design for a correlator access code generator module which they are used for setting up a connection between units, a packet decision, a clock syncronization, by FPGA. The orrelator module which is composed of the Wallace Tree's CSA and threshold value decision device decides useful a packet and syncronizes a clock, after it correlates an input signal of 1 Mbps transmission rate by a sliding window. An access code generator module which is composed of a BCH (Bose-Chadhuri-Hocquenghem) cyclic encoder and control device was designed according as a four steps' generation process proposed in the bluetooth standard. The pseudo random sequence which solves syncronization problem saved a voluntary device Proposed the module was designed by VHDL. An simulation and test are inspected by Xilinx FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.6
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• pp.910-915
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• 2018

The precise time, which is an essential element of the Global Navigation Satellite System (GNSS), such as US GPS, GLONASS in Russia, Galileo in Europe, and Beidou in China, is an important foundation for various economic activities around the world. Communication systems, power grids, IoT, Cloud computing and financial networks operate based on the precise time not only for the operating principles, but also for the synchronization and operational efficiency between tasks. In this paper, we introduce the Atomium software for the first time in South Korea. Atomium was developed by ORB in Belgium to calculate the clock error(clock solution) with GNSS signal observation data based on PPP method. The observation data is provided by Korea Research Institute of Standards and Science(KRISS). The results of MJD57106 with Atomium software are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.91-98
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• 2015

As one of solutions to obtain efficient use of limited spectrum resource, we suggest a methodology for the co-channel multi-site radar operations with a shifted linear frequency modulation (SLFM) based on GPS clock. The proposed algorithm is that we find a candidate set of SLFM signals with the minimum acceptable level of the correlation from the cross-correlation characteristics among selected SLFM signals. To verify the proposed methodology, numerical analysis has been accomplished for several radars operating in the same channel with a sawtooth or triangle LFM signal. The computational results of detected distances as well as range profiles are also examined for interference, noise, and algorithm limitation including the error of clock synchronization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.461-463
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• 2018

In this paper, we have studied the devices needed for long distance wireless transmission of SDH network. This devices propose wireless transmission and measurement method of STM-1(basic transmission unit of SDH method) signal and 200Mbps synchronous ethernet. The synchronous clock recovery function is provided for STM-N transmission and synchronous ethernet transmission, and spare clock switching function is designed for stable synchronization. In addition, we discussed the measurement method of STM-N and synchronous Etherent communication method in wireless transmission section.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.9-14
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• 2006

Galileo is the European Global Navigation Satellite System, under civilian control, and consists on a constellation of medium Earth orbit satellites and its associated ground infrastructure. Galileo will provide to their users highly accurate global positioning services and their associated integrity information. The elements in charge of the computation of Galileo navigation and integrity information are the OSPF (Orbit Synchronization Processing Facility) and IPF (Integrity Processing Facility), within the Galileo Ground Mission Segment (GMS). Navigation algorithms play a key role in the provision of the Galileo Mission, since they are responsible for computing the essential information the users need to calculate their position: the satellite ephemeris and clock offsets. Such information is generated in the Galileo Ground Mission Segment and broadcast by the satellites within the navigation signal, together with the expected a-priori accuracy (SISA: Signal-In-Space Accuracy), which is the parameter that in fault-free conditions makes the overbounding the predicted ephemeris and clock model errors for the Worst User Location. In parallel, the integrity algorithms of the GMS are responsible of providing a real-time monitoring of the satellite status with timely alarm messages in case of failures. The accuracy of the integrity monitoring system is characterized by the SISMA (Signal In Space Monitoring Accuracy), which is also broadcast to the users through the integrity message.

• Journal of Navigation and Port Research
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• v.40 no.1
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• pp.15-20
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• 2016

In this study we measured a differential ASF to improve the accuracy of time synchronization with the signal transmitted from Pohang 9930M Loran station. We obtained the differential ASF which is calculated from a difference of the TOA measurements between KRISS and Chungnam National University(CNU), and KRISS and National Maritime PNT Office respectively. The TOA measurement at KRISS was measured by UTC(KRIS) reference clock and other sites were measured by atomic clocks respectively. The time variations of differential ASF measurements at CNU and National Maritime PNT Office were within $0.1{\mu}s$ and $0.05{\mu}s$ respectively. And we found the time variations of $0.1{\mu}s$ depending on the surrounding radio-wave environments from the differential ASF measurements of 60 minute moving averages. We can improve the accuracy of time synchronization of the local clock to within 10 ns by compensating the differential ASF through removing the common component of ASF. And we measured the absolute ASF between the Pohang transmit station and KRISS by the measurement technique of absolute time delay using a cesium atomic clock. The average ASF between two points is about $3.5{\mu}s$.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.35-43
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• 1998

This study has been experimented the characteristics of synchronous oscillator for clock recovery of Direct Sequence/Spread Spectrum(DS/SS) communication. When external wave is not provided, The Synchronous Oscillator(SO) oscillates at its natural frequency. As soon as external signal is applied, the SO starts tracking the external frequency which can be sinusoidal, pulsed or some other waveform. Thus, the output is synchronized with the range of wide tracking bandwidth to the external frequency Specifically, the SO also posses frequency division and multiplication capability. All of these indicate that the SO can overcome difficulties to get synchronization in coherent digital communication systems. We make a practical application of DS/SS communication with study on the synchronous properties of SO. As the result, we have a good performance.