• Journal of Power Electronics
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• v.15 no.3
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.2
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• pp.148-152
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• 2010

The superconducting fault current limiter (SFCL) applied into the neural line of a power system, which can limit the unsymmetrical fault current from the single-line ground fault or the double-line ground fault, was reported to be the effective application location of the SFCL in a power system. However, the limiting operation for the symmetrical fault current like the triple line-ground fault is not effective because of properties of the balanced three-phase system. In this paper, the limiting method of the symmetrical fault current in a power system with a SFCL applied into neutral line was suggested. Through the short-circuit experiments of the three-phase fault types for the suggested method, the fault current limiting and recovery characteristics of the SFCL in the neutral line were analyzed and the effectiveness of the suggested method was described.

• Journal of Power Electronics
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• v.15 no.3
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• pp.621-633
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• 2015

This paper proposes the analysis and design of a DC-side symmetrical zero-current-switching (ZCS) Class-D current-source driven resonant rectifier to improve the low power-factor and high line current harmonic distortion of lighting applications. An analysis of the junction capacitance effect of Class-D ZCS rectifier diodes, which has a significant impact on line current harmonic distortion, is discussed in this paper. The design procedure is based on the principle of the symmetrical Class-D ZCS rectifier, which ensures more accurate results and provides a more systematic and feasible analysis methodology. Improvement in the power quality is achieved by using the output characteristics of the DC-side Class-D ZCS rectifier, which is inserted between the front-end bridge-rectifier and the bulk-filter capacitor. By using this symmetrical topology, the conduction angle of the bridge-rectifier diode current is increased and the low line harmonic distortion and power-factor near unity were naturally achieved. The peak and ripple values of the line current are also reduced, which allows for a reduced filter-inductor volume of the electromagnetic interference (EMI) filter. In addition, low-cost standard-recovery diodes can be employed as a bridge-rectifier. The validity of the theoretical analysis is confirmed by simulation and experimental results.

• Journal of Power Electronics
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• v.12 no.3
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• pp.429-438
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• 2012

This paper presents the use of a novel, single-stage high-power-factor electronic ballast with a symmetrical class-DE low-$d{\upsilon}$/$dt$ resonant rectifier as a power-factor corrector for fluorescent lamps. The power-factor correction is achieved by using a bridge rectifier to utilize the function of a symmetrical class-DE resonant rectifier. By employing this topology, the peak and ripple values of the input current are reduced, allowing for a reduced filter inductor volume of the EMI filter. Since the conduction angle of the bridge rectifier diode current was increased, a low-line current harmonic and a power factor near unity can be obtained. A prototype ballast, operating at an 84-kHz fixed frequency and a 220-$V_{rms}$, 50-Hz line input voltage, was utilized to drive a T8-36W fluorescent lamp. Experimental results are presented which verify the theoretical analysis.

• Journal of the Korean Ceramic Society
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• v.53 no.5
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• pp.489-493
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• 2016

Scandia ($Sc2O_3$)-stabilized zirconia (ScSZ) electrolyte-supported symmetrical solid oxide electrolyzer cells (SOECs), in which lanthanum strontium cobalt ferrite (LSCF)-gadolinia ($Gd_2O_3$)-doped ceria (GDC) composite materials are used as both the cathode and anode, were fabricated and their high temperature steam electrolysis (HTSE) performance was investigated. Current density-voltage curves were obtained for cells operated in 10% $H_2O$/90% Ar at 750, 800, and $850^{\circ}C$. It was possible to determine the ohmic, cathodic, and anodic contributions to the total overpotential using the three-electrode technique. The HTSE performance was significantly improved in the symmetrical cell with LSCF-GDC electrodes compared to the cell consisting of an Ni-YSZ cathode and LSCF-GDC anode. It was found that the overpotential due to the LSCF-GDC cathode largely decreased and, at a given current density, the total cell voltage decreased, which resulted in the enhanced hydrogen production rate in the symmetrical cell.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.3
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• pp.219-226
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• 1992

In this study, Kalman filtering theory is applied to the estimation of symmetrical components from fault voltage and current signal when it comes to faults with the power system. An algorithm for estimating fault location accurately and quickly by calculating the symmetrical components from the extracted fundamental voltage phasor and current phasor is presented. Also, to confirm the validity of digital distance relaying techniques using Kalman filtering, the experimental results obtained by using the digital simulation of power system is shown.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.22-24
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• 2001

This paper presents a fault phase selection algorithm for transmission line protection by means of the symmetrical components. Accurate fault phase selection is necessary for collect functioning of transmission line relaying, particularly in Extra High Voltage (EHV) networks. The conventional phase selection algorithm used the phase difference between positive and negative sequence current excluding load current. But, it is difficult to abstract only fault current since we can not know the time which a fault occurs. The proposed algorithm can select the accurately fault phase using fault current contained pre-fault current.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.2
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• pp.119-126
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• 1999

Current transformer (CT) saturation may cause a variety of protective relays to malfunction. The conventional CT is designed that it can carry up to 20 times the rated current without exceeding 10% ratio error. However, the possibility of CT saturation still remains if the fault current contains substantial amounts of ac and/or dc components. This paper presents a design method of iron-cored CTs for use with protective relays to prevent CT saturation. The proposed design method determines the core cross section of the CT; it employs the transient dimensioning factor to consider relay's operating time (duty cycle) and dc component as well as ac components contained in the fault current, and symmetrical short-circuit current factor to consider as well as ac components contained in the fault current, and symmetrical short-circuit current factor to consider the biggest fault current. The method designs the cross section of CTs in cases of reclosure and no reclosure.