• Title/Summary/Keyword: Symmetric Encryption

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Security Analysis against RVA-based DPA Countermeasure Applied to $Eta_T$ Pairing Algorithm (RVA 기반의 페어링 부채널 대응법에 대한 안전성 분석)

  • Seo, Seog-Chung;Han, Dong-Guk;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.21 no.2
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    • pp.83-90
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    • 2011
  • Recently, pairings over elliptic curve have been applied for various ID-based encryption/signature/authentication/key agreement schemes. For efficiency, the $Eta_T$ pairings over GF($P^n$) (P = 2, 3) were invented, however, they are vulnerable to side channel attacks such as DPA because of their symmetric computation structure compared to other pairings such as Tate, Ate pairings. Several countermeasures have been proposed to prevent side channel attacks. Especially, Masaaki Shirase's method is very efficient with regard to computational efficiency, however, it has security flaws. This paper examines closely the security flaws of RVA-based countermeasure on $Eta_T$ Pairing algorithm from the implementation point of view.

Novel Secure Hybrid Image Steganography Technique Based on Pattern Matching

  • Hamza, Ali;Shehzad, Danish;Sarfraz, Muhammad Shahzad;Habib, Usman;Shafi, Numan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.3
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    • pp.1051-1077
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    • 2021
  • The secure communication of information is a major concern over the internet. The information must be protected before transmitting over a communication channel to avoid security violations. In this paper, a new hybrid method called compressed encrypted data embedding (CEDE) is proposed. In CEDE, the secret information is first compressed with Lempel Ziv Welch (LZW) compression algorithm. Then, the compressed secret information is encrypted using the Advanced Encryption Standard (AES) symmetric block cipher. In the last step, the encrypted information is embedded into an image of size 512 × 512 pixels by using image steganography. In the steganographic technique, the compressed and encrypted secret data bits are divided into pairs of two bits and pixels of the cover image are also arranged in four pairs. The four pairs of secret data are compared with the respective four pairs of each cover pixel which leads to sixteen possibilities of matching in between secret data pairs and pairs of cover pixels. The least significant bits (LSBs) of current and imminent pixels are modified according to the matching case number. The proposed technique provides double-folded security and the results show that stego image carries a high capacity of secret data with adequate peak signal to noise ratio (PSNR) and lower mean square error (MSE) when compared with existing methods in the literature.

Design and Implementation of a 128-bit Block Cypher Algorithm SEED Using Low-Cost FPGA for Embedded Systems (내장형 시스템을 위한 128-비트 블록 암호화 알고리즘 SEED의 저비용 FPGA를 이용한 설계 및 구현)

  • Yi, Kang;Park, Ye-Chul
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.7
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    • pp.402-413
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    • 2004
  • This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

A Design of an AMI System Based on an Extended Home Network for the Smart Grid (스마트 그리드를 위한 확장 홈 네트워크 기반의 AMI 시스템 설계)

  • Hwang, Yu-Jin;Lee, Kwang-Hui
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.7
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    • pp.56-64
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    • 2012
  • A smart grid is the next generation power grid which combines the existing power grid with information technology, so an energy efficient power grid can be provided. In this paper, in order to build an efficient smart grid an AMI system, which gears with the existing home network and provides an user friendly management function, is proposed. The proposed AMI system, which is based on an extended home network, consists of various functional units; smart meters, communication modules, home gateway, security modules, meter data management modules (MDMM), electric power application modules and so on. The proposed home network system, which can reduce electric power consumption and transmit data more effectively, is designed by using IEEE 802.15.4. The extended home gateway can exchange energy consumption information with the outside management system via web services. The proposed AMI system is designed to enable two-way communication between the home gateway and MDMM via the Internet. The AES(Advanced Encryption Standard) algorithm, which is a symmetric block cipher algorithm, is used to ensure secure information exchange. Even though the results in this study could be limited to our experimental environment, the result of the simulation test shows that the proposed system reduces electric power consumption by 4~42% on average compared to the case of using no control.