• The Transactions of the Korean Institute of Power Electronics
• /
• v.21 no.3
• /
• pp.260-266
• /
• 2016

A new method for the current ripple reduction of a three-phase interleaved bidirectional DC-DC converter is proposed. The converter used in this study operates in discontinuous mode to minimize the switching losses. All the switches are turned on at ZVS and ZCS conditions, and turned off at ZVS condition. The charging and discharging power of the battery is controlled by varying the switching frequency while maintaining the discontinuous mode operation. A 3 kW 20 kHz power converter is designed and implemented. Simulation and experimental results show the validity of the proposed method. The proposed control method can be used to reduce the battery ripple current significantly.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.50-57
• /
• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.1
• /
• pp.68-75
• /
• 2012

This paper presents a comparative analysis of the parallel operation of different switches in a DC/DC converter. In high power applications, multi-switch PWM power conditioners may be preferred despite a higher component count, due to the absence of low frequency filters, reduced switching losses and fault tolerance. The paper demonstrates how current sharing (CSH) and time sharing (TSH) lead to the reduction of switching stress in the parallel operation of switches in any converter. The solutions proposed in this study can be applied on different scales to other power conditioners for DC/DC converter systems. Discussions of the concepts, hypotheses and computer simulations are verified by 1 kW experimental results.

• Journal of Power Electronics
• /
• v.12 no.2
• /
• pp.249-257
• /
• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.16 no.1
• /
• pp.1-7
• /
• 2008

This paper presents electromagnetic interference(EMI) suppression method applied on the direct current(DC) motor driver for power tail gate control. EMI noise is generated by the fast switching of power devices connected to electric loads. It has become a matter of concern because of the vast increase in the number and sophistication of electronic system in automotive environment. The proposed EMI reduction method is based on the principle of reducing the transient speed of power devices by changing the parameters of the driver circuit related to the power MOSFET. In this paper, power losses were calculated by loss equations and thermal simulation was used to evaluate the effect on printed circuit board. Based on these results, the DC motor driver was fabricated and tested. The proposed method can help to design a DC motor driver which allows it to obtain an acceptable compromise between power losses and EMI.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1018-1019
• /
• 2015

Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.60 no.1
• /
• pp.48-52
• /
• 2011

Over the years, traditionally, six-switch three-phase inverters have been widely utilized for variable speed alternating current motor drives. Recently, some efforts have been made on the application of four-switch three phase inverter for uninterruptible power supply and variable speed drives. This is due to some advantages of the four-switch three phase inverter over the conventional six-switch three-phase inverters such as reduced price due to reduction in number of switches, reduced switching losses, reduced number of interface circuits to supply logic signals for the switches, simpler control algorithms to generate logic signals, less chances of destroying the switches due to lesser interaction among switches, and less real-time computational burden. However such as slow di/dt and speed limitation, are the inherent characteristics and main drawbacks of the four-switch configuration. Those problems can be overcome in conjugation with Voltage-doublers which has additional advantage, such as unity power factor correction.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.268-269
• /
• 2017

This paper presents an improved current control strategy for a three-phase grid-connected inverter under distorted grid conditions. Distorted grid condition is undesirable due to negative effects such as power losses and heating problem in electrical equipments. To enhance the power quality of distributed generation systems under such a condition, a modulated finite control set - model predictive control (MFCS-MPC) scheme will be proposed, in which the optimal switching signals of inverter are chosen by online basis using the principle of current error minimization. In addition, the moving average filter (MAF) is used to improve the phase-lock loop in order to obtain the harmonic-free reference currents on the stationary frame. The usefulness of the proposed MFCS-MPC method is proved by the comparative simulation results under different operating conditions.

• Journal of Power Electronics
• /
• v.10 no.4
• /
• pp.365-373
• /
• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.2
• /
• pp.329-337
• /
• 2016

With the increasing deployment of distributed generators in the distribution system, a very large search space is required when dynamic programming (DP) is applied for the optimized dispatch schedules of voltage and reactive power controllers such as on-load tap changers, distributed generators, and shunt capacitors. This study proposes a new optimal voltage and reactive power scheduling method based on dynamic programming with a heuristic searching space reduction approach to reduce the computational burden. This algorithm is designed to determine optimum dispatch schedules based on power system day-ahead scheduling, with new control objectives that consider the reduction of active power losses and maintain the receiving power factor. In this work, to reduce the computational burden, an advanced voltage sensitivity index (AVSI) is adopted to reduce the number of load-flow calculations by estimating bus voltages. Moreover, the accumulated switching operation number up to the current stage is applied prior to the load-flow calculation module. The computational burden can be greatly reduced by using dynamic programming. Case studies were conducted using the IEEE 30-bus test systems and the simulation results indicate that the proposed method is more effective in terms of saving electric charges and improving the voltage profile than loss minimization.