• Journal of IKEEE
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• v.23 no.3
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• pp.865-872
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• 2019

We developed a one-dimensional Ar fluid model running in DC-type applied voltage with a sine and a pulse waveform at the atmosphere pressure. We investigated the light emissions and efficiencies of ${\lambda}_{128nm}$, ${\lambda}_{727nm}$, ${\lambda}_{912nm}$ and ${\lambda}_{966nm}$ from the Ar excited particles. From the results, the light emission of ${\lambda}_{128nm}$ and ${\lambda}_{727nm}$ in the applied voltage with a sine waveform were almost two times as in DC voltage type. The shorter the switching time of applied voltage was, the more the light emissions of ${\lambda}_{128nm}$ and ${\lambda}_{727nm}$ were. We discussed the power consumption and Joule heating by charged particles.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.5
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• pp.383-388
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• 2021

Air-breathing engines used in aircraft have a performance limit as the altitude increases, and this determines the service and absolute ceiling altitude. The method of maintaining altitude and speed in a fixed-wing aircraft in level flight using classical control method is generally using thrust for speed increase/deceleration and pitch attitude for altitude increase/decrease. If this method is used near the service ceiling altitude, increasing the pitch to reduce the altitude error results in a speed reduction. Therefore, it is necessary to use a control method that maintains the speed first using the pitch attitude. Especially in the case of unmanned aerial vehicles, these two methods should be automatically available at the right time. In this paper, we propose a method of switching the speed and altitude maintenance algorithm near service ceiling altitude.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.6
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• pp.1892-1912
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• 2022

With the massive demand and growth of cloud computing, virtualization plays an important role in providing services to end-users efficiently. However, with the increase in services over Cloud Computing, it is becoming more challenging to manage and run multiple Virtual Machines (VMs) in Cloud Computing because of excessive power consumption. It is thus important to overcome these challenges by adopting an efficient technique to manage and monitor the status of VMs in a cloud environment. Reduction of power/energy consumption can be done by managing VMs more effectively in the datacenters of the cloud environment by switching between the active and inactive states of a VM. As a result, energy consumption reduces carbon emissions, leading to green cloud computing. The proposed Efficient Dynamic VM Scheduling approach minimizes Service Level Agreement (SLA) violations and manages VM migration by lowering the energy consumption effectively along with the balanced load. In the proposed work, VM Scheduling for Efficient Dynamically Migrated VM (VMS-EDMVM) approach first detects the over-utilized host using the Modified Weighted Linear Regression (MWLR) algorithm and along with the dynamic utilization model for an underutilized host. Maximum Power Reduction and Reduced Time (MPRRT) approach has been developed for the VM selection followed by a two-phase Best-Fit CPU, BW (BFCB) VM Scheduling mechanism which is simulated in CloudSim based on the adaptive utilization threshold base. The proposed work achieved a Power consumption of 108.45 kWh, and the total SLA violation was 0.1%. The VM migration count was reduced to 2,202 times, revealing better performance as compared to other methods mentioned in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.2
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• pp.143-150
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• 2023

Underwater wireless communication is a challenging issue for realizing the smart aqua-farm and various marine activities for exploring the ocean and environmental monitoring. In comparison to acoustic and radio frequency technologies, the visible light communication is the most promising method to transmit data with a higher speed in complex underwater environments. To send data at a speedier rate, high-performance photodetectors are essentially required to receive blue and/or cyan-blue light that are transmitted from the light sources in a light-fidelity (Li-Fi) system. Here, we fabricated high-performance organic phototransistors (OPTs) based on P-type donor polymer (PTO2) and N-type acceptor small molecule (IT-4F) blend semiconductors. Bulk-heterojunction (BHJ) PTO2:IT-4F photo-active layer has a broad absorption spectrum in the range of 450~550 nm wavelength. Solution-processed OPTs showed a high photo-responsivity >1,000 mA/W, a large photo-sensitivity >10³, a fast response time, and reproducible light-On/Off switching characteristics even under a weak incident light. BHJ organic semiconductors absorbed photons and generated excitons, and efficiently dissociated to electron and hole carriers at the donor-acceptor interface. Printed and flexible OPTs can be widely used as Li-Fi receivers and image sensors for underwater communication and underwater internet of things (UIoTs).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1081-1086
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• 2023

The rapid growth and increasing complexity of modern networks have highlighted the limitations of traditional network architectures. The emergence of SDN (Software-Defined Network) in response to these challenges has changed the existing network environment. The SDN separates the control unit and the data unit, and adjusts the network operation using a centralized controller. However, this structure has also recently caused a huge amount of traffic due to the rapid spread of numerous Internet of Things (IoT) devices, which has not only slowed the transmission speed of the network but also made it difficult to ensure quality of service (QoS). Therefore, this paper proposes a method of load distribution by switching the IP and any server (processor) from the existing data processing scheduling technique, RR (Round-Robin), to mapping when a large amount of data flows in from a specific IP, that is, server overload and data loss.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.679-684
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• 2005

There are a few representative wireless network access technologies used widely. WWAN is celluar based telecommunication networks supporting high mobility, WLAN ensures high data rate within hotspot coverage, and WDMB support both data and broadcasting services correspondingly. However, these technologies include some limitations especially on the mobility, data rate, transmission direction, and so on. In order to overvome these limitations, there are various studies have been proposed in terms of 'Vortical Handoff' that offers seamless connectivity by switching active connection to the appropriate interface which installed in the mobile devices. In this paper, we propose the interface selection algorithm and network architecture to maximize the life time of entire system by minimizing the unnecessary energy consumption of another interfaces such as WLAN, WDMB that are taken in the user equipment. In addition, by using the results of analyzing multiple types of traffic and managing user buffer as a metric for vertical handoff, we show that the energy efficiency of our scheme is $75\%$ and $34\%$ than typical WLAN for WDMB and WLAN preferred schemes, correspondingly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.