• 제목/요약/키워드: Switching Time

검색결과 1,898건 처리시간 0.026초

Chattering에 의한 위성 탑재체 지향성능저하 최소화를 위한 반능동제어기법 성능분석 (Performance Investigation of Semi-Active Control Logic to Minimize a Pointing Performance Degradation of On-Board Payload by Chattering Effects)

  • 오현웅;최영준
    • 한국항공우주학회지
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    • 제38권9호
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    • pp.882-889
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    • 2010
  • 수동형 진동제어 방식과 같이 시스템이 안정되며, 수동형에 비해 높은 제진 효과가 기대되는 반능동 진동제어 방식은 시스템의 안정화가 요구되는 우주구조물의 제진방법에 유효한 진동제어 방식중 하나이다. On-Off 제어방식에 근거한 반능동 제어는 On-Off 스위칭 시에 전달력의 불연속성으로 인한 chattering을 발생시킬 수 있으며, 이는 탑재체 구조물의 고유진동수와의 커플링으로 인하여 지향성능을 저하시키는 원인으로 작용할 수 있다. 본 논문에서는 chattering 영향 최소화를 통한 지향성능향상을 목적으로 LQ(Linear Quadratic)이론에 기반한 가변 감쇠형 반능동 제어기법을 제안하였다. 시뮬레이션 결과는 본 논문에서 제안한 반능동 제어기법은 기존의 skyhook와 LQ를 기반으로 하는 Bang-Bang 반능동 제어기법과 비교하여 높은 진동절연 성능을 나타내고 있다.

Electrical Characteristic of Power MOSFET with Zener Diode for Battery Protection IC

  • Kim, Ju-Yeon;Park, Seung-Uk;Kim, Nam-Soo;Park, Jung-Woong;Lee, Kie-Yong;Lee, Hyung-Gyoo
    • Transactions on Electrical and Electronic Materials
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    • 제14권1호
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    • pp.47-51
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    • 2013
  • A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

DFIG 풍력발전기가 연계된 배전선로의 고조파 공진 특성에 관한 연구 (A Study on Harmonic Resonance in a DFIG Wind Turbine-generator Connected to a Distribution Power Line)

  • 최형주;이흥호
    • 전기학회논문지
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    • 제62권10호
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    • pp.1383-1389
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    • 2013
  • There were telecommunication noise and malfunctions of the electronic devices occurred over a wide area due to the high harmonic voltage and/or current levels of the Back-to-back converter in the DFIG wind power system even though the magnitude of all harmonics is within the international standards. The triangular carrier signals of the PWM used in the power converter system is related to the telecommunication noise because they are in the range of audible frequencies and amplified by a variety of the standing waves that were excited by harmonic voltage sources in the weak grid system such as a long distance distribution transmission lines. This paper describes the characteristics of the harmonics in the wind turbine-generator, numerical analysis and simulation of the harmonics resonance phenomena in the distribution lines as well as measuring induced voltage of the telecommunication lines in parallel with power lines in order to verify the root cause of the telecommunication noise. These noise problems can occur in a wind turbine power system with a non-linear converter at any time, as well as photovoltaic power system. So, the preliminary review of suitable filter devices and switching frequencies of the PWM have to be required by considering the stability of the controller at the design stage but as part of the measures the effect of the telecommunication cable shields was analyzed by comparing the measured data between multi-conductor with/without shields so as to attenuate the sources of the harmonics voltage induced into the telecommunication lines and to apply the most cost-effective measures in the field.

순환적 최적우선탐색을 이용한 배전계통의 정전복구 (Service Restoration In Distribution Networks Using Cyclic Best-First Search)

  • 최상열
    • 조명전기설비학회논문지
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    • 제18권5호
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    • pp.162-168
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    • 2004
  • 정전복구 문제는 배전계통에서 고장이 발생한 겨우 사고 구간 이후의 비 고장 정전구간내의 부하를 적절한 스위칭을 통하여 인접된 건전피더로 빠른 시간 내에 절체 시키는 것이며 이때 방사상 선로구성, 전압, 전류 등의 제약조건들이 만족되어야 한다. 본 논문에서는 건전피더들이 고장 발생 직후 계통으로 공급하여야 할 부하의 총량을 규정하는 함수와 순환적 최적우선탐색을 이용하여 사고 발생 시 단지 정전의 복구뿐만 아니라 부하의 균등화까지도 함께 수행되는 효율적인 정전복구 알고리즘을 제시한다. 제시되는 알고리즘은 건전피더들이 고장 발생 직후 계통으로 공급하여야 할 부하의 총량을 규정하는 함수로부터 각 피더들이 공급하여야 할 목표치를 제안하고 또한 지수의 목적 값을 만족하는 스위칭을 찾기 위하여 순환적 최적우선 탐색법을 이용한다. 본 논문에서는 제시한 알고리즘을 실제로 서울의 K지사에서 윤용하고 있는 108모선에 적용하여 결과를 도출 했으며 그 결과 제안된 알고리즘을 이용할 경우에 적은 탐색 횟수로 정전이 복구됨과 동시에 건전 선로간의 부하가 균등화되었음을 입증하였다.

저전압 플래시메모리를 위한 SONOS 비휘발성 반도체기억소자에 관한 연구 (A Study on SONOS Non-volatile Semiconductor Memory Devices for a Low Voltage Flash Memory)

  • 김병철;탁한호
    • 한국정보통신학회논문지
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    • 제7권2호
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    • pp.269-275
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    • 2003
  • 저전압 프로그래밍이 가능한 플래시메모리를 실현하기 위하여 0.35$\mu\textrm{m}$ CMOS 공정 기술을 이용하여 터널링산화막, 질화막 그리고 블로킹산화막의 두께가 각각 2.4nm, 4.0nm, 2.5nm인 SONOS 트랜지스터를 제작하였으며, SONOS 메모리 셀의 면적은 1.32$\mu$$m^2$이었다. 질화막의 두께를 스케일링한 결과, 10V의 동작 전압에서 소거상태로부터 프로그램상태로, 반대로 프로그램상태에서 소거상태로 스위칭 하는데 50ms의 시간이 필요하였으며, 최대 메모리윈도우는 1.76V이었다. 그리고 질화막의 두께를 스케일링함에도 불구하고 10년 후에도 0.5V의 메모리 윈도우를 유지하였으며, 105회 이상의 프로그램/소거 반복동작이 가능함을 확인하였다. 마지막으로 부유게이트 소자에서 심각하게 발생하고있는 과도소거현상이 SONOS 소자에서는 나타나지 않았다.

보행 방향 및 상태 분석을 위한 병렬 가우스 과정 (Parallel Gaussian Processes for Gait and Phase Analysis)

  • 신봉기
    • 정보과학회 논문지
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    • 제42권6호
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    • pp.748-754
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    • 2015
  • 본 연구에서는 다중 상태 변수의 인수 HMM을 일반화하여 연속 은닉 변수와 이산 은닉 변수가 결합된 순차 상태 추정 모형을 제안하고 이에 기반한 보행 동작 모형을 설계한다. 유한 상태의 이산변수는 마르코프 연쇄 구조로 보행의 동역학적 특성을 표현하고 각 이산 상태에 대해 연속 변수를 독립변수로 한 가우스 과정을 정의한다. 마르코프 상태 천이는 여러 가우스 과정 사이의 스위칭을 제어하며 각 가우스 과정은 동일한 자세의 회전 또는 다양한 시각을 표현한다. 온라인 필터링 추론을 위해 입자 필터 방식의 추론 알고리듬도 제시한다. 이 알고리듬은 입력 벡터 열이 주어졌을 때 이들 병렬적 가우스 과정을 동적으로 갈아타는 스위칭 궤적을 디코딩 해준다. 실험 결과 비선형적 보행자 비디오 영상을 보행방향과 보행 상태의 열로 분리하며 매우 직관적인 해석을 할 수 있음을 보였다.

8인치 Si Power MOSFET Field Ring 영역의 도핑농도 변화에 따른 전기적 특성 비교에 관한 연구 (Characterization and Comparison of Doping Concentration in Field Ring Area for Commercial Vertical MOSFET on 8" Si Wafer)

  • 김권제;강예환;권영수
    • 한국전기전자재료학회논문지
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    • 제26권4호
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    • pp.271-274
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    • 2013
  • Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

음향 공명 제거 및 조광 제어가 가능한 1kW 메탈 핼라이드 램프용 전자식 안정기 설계 (The Design of Acoustic Resonance Free and Dimmable Electronic Ballast for 1kW MHL)

  • 이봉진;박종연;김기남
    • 전기학회논문지
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    • 제57권10호
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    • pp.1782-1789
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    • 2008
  • This paper presents the design of acoustic resonance(AR) free and dimmable electronic ballast for 1kW Metal-Halide Lamp(MHL). The proposed Ballast consists of a Full-Bridge(FB) rectifier, a passive power factor correction(PFC) circuit, a full-bridge inverter, an ignitor using LC resonance and a control circuit for frequency modulation and dimming control. Whereas a passive PFC provides advantages in terms of high reliability and low cost for constructing the circuit, it is difficult to supply a stable voltage because of the output voltage ripple that occurs with a period of 120Hz. Although the ballast can be designed with a small size and a light weight if it is driven at a switching frequency between 1 and 100 kHz, AR will occur if the eigenvalue frequency of the lamp coincides with the inverter's operation frequency. The operation frequency was modulated in real time according to the output voltage ripple to compensate for the variation in power supplied to the lamp and eliminate AR. For dimming, the method, which modulated drive frequency of FB inverter using the control of DC level by microprocessor, was used. The Dimming ranged at least from 600W to 1kw as rated power of the lamp with 4 stages. Performance of the proposed technique was validated through numerical analysis, computer simulation using Pspice and by applying it to an electronic ballast for a prototype 1kW MHL.

Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

  • Sivakumar, M.;Omkumar, S.
    • Journal of Electrical Engineering and Technology
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    • 제13권6호
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    • pp.2479-2484
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    • 2018
  • The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

Two-Stage Fermentation for 2-Ketogluconic Acid Production by Klebsiella pneumoniae

  • Sun, Yuehong;Wei, Dong;Shi, Jiping;Mojovic, Ljiljana;Han, Zengsheng;Hao, Jian
    • Journal of Microbiology and Biotechnology
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    • 제24권6호
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    • pp.781-787
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    • 2014
  • 2-Ketogluconic acid production by Klebsiella pneumoniae is a pH-dependent process, strictly proceeding under acidic conditions. Unfortunately, cell growth is inhibited by acidic conditions, resulting in low productivity of 2-ketogluconic acid. To overcome this deficiency, a two-stage fermentation strategy was exploited in the current study. During the first stage, the culture was maintained at neutral pH, favoring cell growth. During the second stage, the culture pH was switched to acidic conditions favoring 2-ketogluconic acid accumulation. Culture parameters, including switching time, dissolved oxygen levels, pH, and temperature were optimized for the fed-batch fermentation. Characteristics of glucose dehydrogenase and gluconate dehydrogenase were revealed in vitro, and the optimal pHs of the two enzymes coincided with the optimum culture pH. Under optimum conditions, a total of 186 g/l 2-ketogluconic acid was produced at 26 h, and the conversion ratio was 0.98 mol/mol. This fermentation strategy has successfully overcome the mismatch between optimum parameters required for cell growth and 2-ketogluconic acid accumulation, and this result has the highest productivity and conversion ratio of 2-ketogluconic and produced by microorganism.