• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.691-699
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• 2004

SRM(Switched Reluctance Motor) drives require the accurate position information of the rotor. These informations are generally provided by a tacho generator or digital shaft-position encoder These speed sensors lower the system reliability and require special attention to noise. This paper describes a new approach to estimating SRM speed from measured terminal voltages and currents for speed sensorless control. The described method is based on the sliding mode observer. The rotor speed and position observers are estimated by the adaptation law using the real and estimated currents. However, the conventional adaptive sliding mode observer based on the variable structure control theory has some disadvantages that the estimated values including the high-frequency chattering and the steady state error generated due to the infinite feedback gain chosen and the discontinuous control input. To reduce the chattering and steady state error, an integrator is also inserted in the sliding mode observer strategy. The described adaptive sliding mode observer decreases the vibration to the switching hyper-plane of the sliding mode by adding integrator. The described methodology incorporates the Lyapunov algorithm to drive the rotor speed and the stator resistance such that it can overcome the problem of sensitivity in the face of SRM parameter variation. Also, without any mechanical information. The rotor speed of SRM is obtained form adaptive scheme. The described method is verified through the simulation and experiment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.88-96
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• 2016

In this paper, the GaN FET based phase-shift full-bridge dc-dc converter design is implemented. Switch characteristics of GaN FET were analyzed in detail by comparing state-of-the-art Si MOSFET. Owing to the low conduction resistance and parasitic capacitance, it is expected to GaN FET based power conversion system has improved performance. However, GaN FET is vulnerable to electric interference due to the relatively low threshold voltage and fast switching transient. Therefore, it is necessary to consider PCB layout to design GaN FET based power system because PCB layout is the main reason of stray inductance. To reduce the electric noise, gate voltage of GaN FET is analyzed according to operation mode of phase-shift full-bridge dc-dc converter. Two 600W phase-shifted full-bridge dc-dc converter are designed based on the result to evaluate effects of stray inductance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.65-71
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• 1984

The design formular of optical focusing systems cannot be applied to ultrasonic B scanners, which use broadband pulses instead of continuous wave. In this paper, a calculation method is studied for analyzing the propagation of ultrasonic broadband pulse excited by ultrasonic array transducers. Using the results, seveial design parameters such as the number of transducer elements, delay time, and the focal point are determined to obtain high resolution in the ultrasonic dynamic focusing system. A dynamic focusing system with low-noise switching characteristics; which attains lateral resolution of 2-3mm all along the axial direction up to 18 cm with a 3.5 MHz linear array transducer, was implemented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.2992-3009
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• 2016

The performance of D-MIMO systems is not only affected by multipath fading but also from shadowing fading, as well as path loss. In this paper, we investigate the ergodic capacity of D-MIMO systems operating in non-correlated K fading (Rayleigh/Gamma) channels. With the aid of majorization and Minkowski theory, we derive analytical closed-form expressions of the upper and lower bounds on the ergodic capacity for D-MIMO systems over non-correlated K fading channels, which are quite general and applicable for arbitrary signal-to-noise ratio (SNR) and the number of transceiver antennas. To intuitively reveal the impacts of system and fading parameters on the ergodic capacity, we deduce asymptotic approximations in the high and low SNR regimes. Finally, we pursue the massive MIMO systems analysis for the lower bound and derive closed-form expressions when the number of antennas at BS grows large, and when the number of antennas at transceivers becomes large with a fixed and finite ratio. It is demonstrated that the proposed expressions on the ergodic capacity accurately match with the theoretical analysis.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1227-1232
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• 2008

High-speed train of push-pull type called as G7 train has been developed and chosen as the model of KTX-II which will be operated on Honam Line nexr year. However, the EMU-type high-speed train appeared to be the recent trend that foreign markets have shown. Also, in the near future, a great number of new train sets are needed to accommodate the increased passengers in our country. Thus, development of the high-speed EMU was decided, planned, and started. In the development, included were almost all fundamental key technologies such as noise and vibration reduction in a passenger cabin, running characteristics, aerodynamic analysis, crashworthiness evaluation, EMI/EMC analysis, design of the cooling system for the propulsion control system, enhanced performance of transformer and switching converters, synchronous traction motor with permanent magnets, new design of front nose and ergonomic interiors, application of advanced information technology(IT) and smart sensors and the cost reduction of construction of railway bridges, etc. Each key technologies are carried out as sub-project independently but under the supervision of a project. The project will develop the high advanced level of technologies and provide necessary know-why's and support the team in charge of the development of the high-speed EMU, Hyundai Rotem Co. Ltd. The high-speed EMU will be successfully developed with the support of the project.

• Aerospace Engineering and Technology
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• v.5 no.2
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• pp.67-76
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• 2006

This paper describes the analysis method to define the system specification for conducted EMI environment and verification method to evaluate the conducted EMI performance. Conducted EMI environment is characterized by the electrical power subsystem which is mainly issued by the switching circuit noise, common ground impedance coupling. To define and control these EMI problems, EMI assesment through system analysis are preceded at the early design phase and then EMI reduction methods are applied during the unit/system development phase. System EMC should be carefully controlled and designed in the consideration of EMC safety margin and its performance is fully evaluated at the whole development period.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.11-12
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• 2008

최근 LSI speed의 고속화에 따라, SSN (Simultaneous Switching Noise)이 매우 큰 문제가 되고 있다. 이에 PDN에 대한 많은 해결책들이 제시되고 있으나 가장 저비용 고효율을 지향할 수 있는 방법이 현재 사용되고 있는 유기기판에 Capacitor를 내장하여 로 사용하는 방법이다. Decoupling capacitor를 두께가 밟은 유기기판에 구현하기 위해서는 유전율이 큰 물질을 사용하는 것이 좋은데 본 연구에서는 $BaTiO_3$를 epoxy 에 혼합하여 10um 두께의 필름으로 제작한 후 유기기판 제조 공정에 사용하여 유기기판을 구현하였다. 이렇게 구현된 capacitor 내장 유기기판을 2 stub의 간단한 회로를 구현하여 유전율 등을 측정하였으며, 고주파 전산모사를 통하여 capacitor의 용량 변화에 따른 고주파 특성의 변화를 연구하였다.

• Journal of Power Electronics
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• v.6 no.1
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• pp.45-51
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• 2006

A new high efficiency phase shifted full bridge (PSFB) converter for the power sustaining module of a plasma display panel (PDP) is proposed in this paper. The proposed converter employs a voltage doubler rectifier without an output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the output voltage level. No dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed. Therefore, high efficiency, as well as, a low noise output voltage can be realized. Due to the elimination of the large output inductor, it features a simple structure, lower cost, smaller mass and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell reduces the current stresses of the rectifier diodes. In this paper, operational principles, an analysis of the proposed converter and experimental results are presented.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.8-10
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• 2005

In a general purpose inverter, a dead-time compensation strategy is very important for reducing torque ripples and acoustic noises of motors. However, in the case of small capacity inverter, the accurate dead-time compensation is hard to be obtained because a removal of the switching noise in a feedback current signal is difficult on condition of low-cost implementation. In this paper, the operation characteristics of the general purpose inverter applied the dead time compensation algorithm using an instantaneous back calculation of the phase angle of the current are presented.