• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1063-1066
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• 1992

As the adjustable speed drives by means of PWM inverter are applied to a wider field of industries, the demands for lower acoustic noise caused by modulation is becoming more intense. With the development of high speed power semiconductor device such as the IGBTs, a higher carrier frequency can be adopted to increase the switching frequency to the supersonic range. The optimal magnitude of this signal is determined so that the sideband components near the carrier frequency are minimized

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1104-1107
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• 1992

Voltage controlled current regulated PWM(pulse width modulation) of VSI (voltage source inverter) is proposed. Adopting one degree of freedom, the voltage, the current controller shows much more improvement than conventional ones not using this method. The voltage controller or this proposal needs load's parameters, torque value, rotational speed. This voltage controller is located at converter part which links AC source and DC bus. With this proposed method, duty ratio of the inverter's switching is nearly unity for all speed and torque range. Hence, this method gets many advantages such as reducing current ripple, thermal loss, and noises and improving control performances. Theoretical approach to this voltage-current controller is performed, and the results are presented.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1172-1175
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• 1992

The conventional adaptive hysteresis band current control technique has disadvantages such that on-line calculation of the hysteresis band is very complex, therefore, the adaptive hysteresis band must be stored in the look-up table. In this paper, a new simplified adaptive hysteresis band current control technique with phase decoupling is presented. The adaptive band is independent of the back EMFs. Using this adaptive band and the phase decoupled current error, the modulation frequency is fixed at nearly constant and the PWM inverter has optimal switching pattern.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.56 no.3
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• pp.136-141
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• 2007

In this paper, a new simple control method for active power filter which can realized the complete compensation of the harmonic currents is proposed. In the proposed scheme, a compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Deadbeat control is employed to control the active power filter. The switching pulse width based SVM(Space Vector Modulation) is adopted so that the current of active power filter is been exactly equal to its reference at the next sampling instant. To compensate the computation delay of digital controller, the prediction of current is achieved by the current observer with deadbeat response.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.259-265
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• 2012

This paper introduces a method for design and implementation of a current controller for boost converter operating in continuous conduction mode (CCM) using a digital signal processor (DSP). A Proportional-Integral (PI) type current controller outputs an average voltage command for inductor, used in the input side of the boost converter, and the duty-ratio of PWM (pulse width modulation) signal for switching device is directly calculated from the average voltage command. The gains of the PI current controller are selected such that the current response characteristics are the same as those of a first-order low-pass filter. The proposed current control scheme is implemented using a DSP based on fixed-point math operations and an experimental study has been performed to validate the proposed method.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.121-122
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• 2014

멀티 레벨 인버터는 높은 출력 전압을 갖으며, 낮은 THD(Total harmonic distortion)를 요구하는 시스템에 적합하다. 그 중 cascaded H-brige 멀티레벨 인버터는 H-bridge 셀별 관리가 쉽고, 레벨 수를 증가시키기 쉽다는 장점 때문에 많이 이용되어 왔다. 본 논문에서는 cascaded H-bridge 인버터의 기존 PI (proportional integral) 제어 기반 PWM (pulse width modulation)기법의 스위칭 패턴과 모델 예측 제어의 스위칭 패턴을 비교하고 모델예측 제어 시 셀 별 스위칭 패턴 균형을 위한 방법을 제안한다.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.11-12
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• 2014

This paper introduces a scaled hardware model for the 10kVA, 1kV, 11-level MMC (Modular Multilevel Converter), which was manufactured in the lab based on computer simulations with PSCAD/EMTDC. Various experiments were conducted to verify the major operation algorithms of MMC. The hardware scaled-model developed in the lab can be utilized for analyzing the operation analysis and performance evaluation of MMC according to the modulation pattern and redundancy operation scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.33-37
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• 1998

For the high power variable speed applications, the DCTLI(diode clamped three-level inverter) have been widely used. This paper describes the analysis of the neutral point current of the DCTLI and the improved space vector-based PWM strategy considering the switching frequency of power devices, that minimizes the fluctuation of the neutral point current in spite of high modulation index region and low power factor. It contributes to decrease the capacitance of dc-link capacitor bank and to increase the neutral point voltage controllable region. Especially, even if second (or even) order harmonic is induced in load current (at this situation, is was investigated that the general control method can not suppress the neutral point voltage variation), this PWM can provide effective control method to suppress the neutral point voltage variation. Various simulation results by means of Matlab/Simulation are presented to verify the proposed PWM.