• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.203-214
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• 2005

The integration of 3G networks and WLANs as complementary has been begun to attract much attention in industry as well as academia. This topic is becoming a burning issue, and one of the key questions which it raises is how to support a seamless vertical handoff. This paper introduces a new network interface selection algorithm for energy-efficient vertical handoff in tightly coupled systems capable of supporting seamless handoff. Our proposed scheme, Wise Interface Selection (WISE) switches the active network interface, after taking into consideration the characteristics of the network interface cards and the current level of data traffic, with the cooperation of the mobile terminals and network. Network interface switching operates independently on both the downlink and the uplink for the purpose of energy conservation. We show through simulation that less energy is consumed with WISE than when only a 3G network or WLAN interface is used, resulting in a longer lifetime for the mobile terminals. In the case of TCP connections, additional throughput gain can also be obtained.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.220-235
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• 2005

Internet Service Quality has been constantly the center of attention to Internet Service Providers. The KII project plan (Korea Information Infrastructure) aims to build broadband backbone networks mainly through optical fiber cables and ATM switches and to Provide the government ministries, local authorities and non-profit organizations with high-speed, highly capable broadband access to these networks at reasonable rates. The KB service model, however, is different from other Internet Service models much in the same way SP (Service Provider) and NP (Network Provider) differ from each other. In this paper, we evaluate KII service according to various customer satisfaction indicators under the methodologies and categories as put forth in both the ACSI (American Customer Satisfaction Index) and SEM (Structural Equation Model). We use a structural equation model (SEM) to demarcate the Korea Information Infrastructure Customer Satisfaction Index (KIICSI) in relation to network service quality. The results of our study suggest some strategies for the KII Project need to be modified and effectively implemented in order to increase the satisfaction level of the KII customers.

• Journal of Internet Computing and Services
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• v.8 no.1
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• pp.33-45
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• 2007

Using switches and sensors informing the current on or off state, this paper suggests a sleeping control and remote monitoring system that not only can recognize the sleeping situations but also can control for keeping an appropriate sleeping situation remotely, And we show an example that this system is applied to the healthcare sleeping mat, Our system comprises the following 3 parts: a part for detecting the sleeping situations, a part for extracting sensing data and sending/receiving the relating situated data, and a part controlling and monitoring the all of sleeping situations. In details, in order to develop our system, we used the touch and pressure-sensitive sensors with On/Off functions for a purpose of the first part, The second part consists of the self-developed embedded board with the socket based communication as well as extracting real-time sensing data. And the third part is implemented by service modules for providing controlling and monitoring functions previously described. Finally, these service modules are implemented by the TMO scheme, one of real-time object-oriented programming models and the communications among them is supported using the TMOSM of distributed real-time middleware.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.27-27
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• 2011

For the design of real applicable molecular devices, current-voltage properties through molecular nanostructures such as metal-molecule-metal junctions (molecular junctions) have been studied extensively. In thiolate monolayers on the gold electrode, the chemical bonding of sulfur to gold and the van der Waals interactions between the alkyl chains of neighboring molecules are important factors in the formation of well-defined monolayers and in the control of the electron transport rate. Charge transport through the molecular junctions depends significantly on the energy levels of molecules relative to the Fermi levels of the contacts and the electronic structure of the molecule. It is important to understand the interfacial electron transport in accordance with the increased film thickness of alkyl chains that are known as an insulating layer, but are required for molecular device fabrication. Thiol-tethered RuII terpyridine complexes were synthesized for a voltage-driven molecular switch and used to understand the switch-on mechanism of the molecular switches of single metal complexes in the solid-state molecular junction in a vacuum. Electrochemical voltammetry and current-voltage (I-V) characteristics are measured to elucidate electron transport processes in the bistable conducting states of single molecular junctions of a molecular switch, Ru(II) terpyridine complexes. (1) On the basis of the Ru-centered electrochemical reaction data, the electron transport rate increases in the mixed self-assembled monolayer (SAM) of Ru(II) terpyridine complexes, indicating strong electronic coupling between the redox center and the substrate, along the molecules. (2) In a low-conducting state before switch-on, I-V characteristics are fitted to a direct tunneling model, and the estimated tunneling decay constant across the Ru(II) terpyridine complex is found to be smaller than that of alkanethiol. (3) The threshold voltages for the switch-on from low- to high-conducting states are identical, corresponding to the electron affinity of the molecules. (4) A high-conducting state after switch-on remains in the reverse voltage sweep, and a linear relationship of the current to the voltage is obtained. These results reveal electron transport paths via the redox centers of the Ru(II) terpyridine complexes, a molecular switch.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.2
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• pp.134-145
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• 2004

With rapid growth in the amount of data transferred on the Internet, traditional storage systems have reached the limits of their capacity and performance. SAN (Storage Area Network), which connects hosts to disk with the Fibre Channel switches, provides one of the powerful solutions to scale the data storage and servers. In this environment, the maintenance of data consistency among hosts is an important issue because multiple hosts share the files on disks attached to the SAN. To preserve data consistency, each host can execute the disk I/O whenever disk read and write operations are requested. However, frequent disk I/O requests cause the deterioration of the overall performance of a SAN cluster. In this paper, we introduce a SANtopia global buffer manager to improve the performance of a SAN cluster reducing the number of disk I/Os. We describe the design and algorithms of the SANtopia global buffer manager, which provides a buffer cache sharing mechanism among the hosts in the SAN cluster. Micro-benchmark results to measure the performance of block I/O operations show that the global buffer manager achieves speed-up by the factor of 1.8-12.8 compared with the existing method using disk I/O operations. Also, File system micro-benchmark results show that SANtopia file system with the global buffer manager improves performance by the factor of 1.06 in case of directories and 1.14 in case of files compared with the file system without a global buffer manager.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.467-478
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• 1999

실시간 태스크의 최악 실행시간을 예측할 때 과예측이 발생하는 원인은, 첫째 프로그램의 동적인 최악 실행 행태를 정적으로 분석하는 것이 근본적으로 어렵기 때문이며, 둘째 최근의 RISC 형태 프로세서에 포함되어 있는 파이프라인 실행 구조와 캐쉬 등이 그러한 정적 분석을 더욱 어렵게 만들기 때문이다. 그런데 기존의 연구에서는 각각의 과예측 원인을 해결하기 위한 방법에 대해서만 언급하고 있을 뿐 분석의 정확도에서 각 원인이 차지하는 비중에 대해서는 언급하고 있지 않다. 이에 본 연구에서는 최악 실행시간 예측시 과예측을 유발하는 원인들, 즉 분석 요소들의 영향을 정량적으로 조사함으로써 기존의 최악 실행시간 분석 기법들이 보완해야 할 방향을 제시하고자 한다. 본 연구에서는 실험이 특정 분석 기법에 의존하지 않도록 하기 위하여 시뮬레이션 방법에 기반한다. 이를 위해 분석 요소별 스위치가 포함된 MIPS R3000 프로세서를 위한 시뮬레이터를 구현하였는데, 각 스위치는 해당 분석 요소에 대한 분석의 정확도 수준을 결정한다. 모든 스위치 조합에 대해서 시뮬레이션을 반복 수행한 다음 분산 분석을 수행하여 어떤 분석 요소가 가장 큰 영향을 끼치는지 고찰한다.Abstract Existing analysis techniques for estimating the worst case execution time (WCET) of real-time tasks still suffer from significant overestimation due to two types of overestimation sources. First, it is unavoidably difficult to predict dynamic behavior of programs statically. Second, pipelined execution and caching found in recent RISC-style processors even more complicate such a prediction. Although these overestimation sources have been attacked in many existing analysis techniques, we cannot find in the literature any description about questions like which one is most important. Thus, in this paper, we quantitatively analyze the impacts of overestimation sources on the accuracy of the worst case timing analysis. Using the results, we can identify dominant overestimation sources that should be analyzed more accurately to get tighter WCET estimations. To make our method independent of any existing analysis techniques, we use simulation based methodology. We have implemented a MIPS R3000 simulator equipped with several switches, each of which determines the accuracy level of the timing analysis for the corresponding overestimation source. After repeating simulation for all of the switch combinations, we perform the variance analysis and study which factor has the largest impact on the accuracy of the predicted WCETs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.356-368
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• 2011

While most of the public radio spectrum bands are allocated to licensed users, cognitive radio has been considered as a promising technology for the efficient spectrum utilization. In this new technology, secondary users opportunistically use the temporally underutilized licensed bands as long as they do not give the harmful interference to primary users. In this paper, we focus on the infra-structured network condition in which the cognitive radio network consists of a cognitive radio base station and multiple secondary users. Upon detecting a primary user, the entire cognitive radio network generally switches to another available channel, even if most of the on-going communications still does not interfere with the primary user. Moreover, the network re-entry process on a new channel causes the service disruption of the on-going communications. For this reason, in this paper, we propose a relaying scheme for efficient frequency usage, in which the secondary user out of the interference range of a primary user performs as a relaying node for the secondary user possibly interfering with a primary user. The entire spectrum switching is not required, and thus, we can avoid the service disruption of the on-going communications as much as possible.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1170-1174
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• 2009

Two frequency-reconfigurable antennas have been designed and combined in a space with limited volume, i.e., 40mm ${\times}$ 20mm ${\times}$ 6mm. Each antenna can be reconfigured to operate at different frequency bands depending on the state of an embedded switch, which is implemented using a PIN diode. The first antenna can be switched between 0.82GHz ${\sim}$ 0.96GHz band (GSM/ CDMA) and 1.7GHz ${\sim}$ 2.17GHz band (DCS/ PCS/ WCDMA), which are cellular bands. The second antenna can be switched between 3.4GHz ${\sim}$ 3.6GHz band (mWiMax) and 2.3GHz ${\sim}$ 2.5GHz, 5.15GHz ${\sim}$ 5.35GHz bands (WiBro/ WLAN 11a/b/g/n), which are connectivity bands. The proposed combined antenna operates both over cellular bands and connectivity bands concurrently. The choice of the operation bands is made independently by the states of the two switches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.