• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.387-390
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• 2005

A This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched- capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft-switching commutation. In the first place, the steady-state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment or set-up in laboratory system or this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.485-488
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• 2000

In this paper dynamic analyses and control design of a step-down switched-capacitor dc-dc converter are presented. Open-loop dynamics of the converter are analyzed using the stage-space averaging technique. A systmatic control design method that offers excellent closed-loop performance for the converter is proposed, The analysis results and dynamic performance of the converter are verified using 18 W experimental converter that delivers a 5V/3.5V output from a 11-16V input source.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1436-1441
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• 1990

Prototype Switched Capacitor 4th order Low pass and Band Pass Filters were Realized and tested. Their capacitor values were determined by using automatic SCF design tool. Each filter was designed to operate in voiceband frequency, and practical solutions to improve its frequency characteristics were given. Experimental results show the validity of automatic SCF design program. Simulation and experimental results were fully compared and optimum design conditions were summarized.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.57-61
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• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier and large filter capacitor connected with DC line terminal. Due to the large capacity of the capacitor, the charged time of capacitor is very short from the AC source. Lead to the bridge rectifiers draws pulsating current from the AC source side, which results in reduction of power factor and low system efficiency. Therefore a novel single-phase SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor with a novel switching topology. The proposed drive circuit consists of one switching part and diode, which can separate the output of AC/DC rectifier from the large capacitor and supply power to SRM alternately, in order to realize the torque ripple reduction and power factor improvement through the switching scheme. In addition, the validity of the proposed method is tested by some simulations and experiments.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1449-1457
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• 2019

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

• KIEE International Transactions on Power Engineering
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• v.3A no.1
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• pp.17-26
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• 2003

In this paper, the comparative steady-state operating performance analysis algorithms of the stand-alone single-phase self-excited induction generator (SEIG) is presented on the basis of the two nodal admittance approaches using the per-unit frequency in addition to a new state variable de-fined by the per-unit slip frequency. The main significant features of the proposed operating circuit analysis with the per-unit slip frequency as a state variable are that the fast effective solution could be achieved with the simple mathematical computation effort. The operating performance results in the simulation of the single-phase SEIG evaluated by using the per-unit slip frequency state variable are compared with those obtained by using the per-unit frequency state variable. The comparative operating performance results provide the close agreements between two steady-state analysis performance algorithms based on the electro-mechanical equivalent circuit of the single-phase SEIG. In addition to these, the single-phase static VAR compensator; SVC composed of the thyristor controlled reactor; TCR in parallel with the fixed excitation capacitor; FC and the thyristor switched capacitor; TSC is ap-plied to regulate the generated terminal voltage of the single-phase SEIG loaded by a variable inductive passive load. The fixed gain PI controller is employed to adjust the equivalent variable excitation capacitor capacitance of the single-phase SVC.

• Journal of information and communication convergence engineering
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• v.15 no.1
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• pp.62-71
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• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.505-512
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• 2011

A novel passive boost power converter forsingle-phaseswitched reluctance motor is presented. A simple passive circuit is proposed comprisingthree diodes and one capacitor. The passive circuitis added in the front-end of a conventional asymmetric converter to obtain high negative bias. Based on this passive network, the terminal voltage of the converter side is a general DC-link voltage level in parallel mode up to a double DC-link voltage level in series mode. Thus,it can suppress the negative torque generation from the tail current and improve the output power. The results of the comparative simulation and experiments forthe conventional and proposed converter verify the performance of the proposed converter.

• Journal of Power Electronics
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• v.13 no.6
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• pp.928-938
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• 2013

This paper proposes a novel control method for a multi-output switched-resonant converter. Output voltage can be regulated against variations in the supply voltage and load by controlling the voltage of the resonant capacitor (pulse amplitude control). Precise control is possible when pulse amplitude control is combined with pulse number control. The converter is analyzed, and design considerations are explained by using examples. Control implementation is described and load regulation and ripples are analyzed by simulation and hardware results. The topology is modified to obtain an additional negative output without any additional hardware other than a diode. The analysis of such a triple output converter with two positive outputs and one negative output is conducted and confirmed. The topology and control scheme are scalable to any number of outputs.