• 대한전자공학회논문지SD
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• 제48권1호
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• pp.50-55
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• 2011

본 논문은 Feedback 적분기 계수를 이용하여 IF 대역의 중심주파수 조절이 가능한 Bandpass SC Sigma-de1ta 변조기를 제안한다. 제안한 구조는 Feedback loop에 적분기를 추가함으로서 동일 차수의 기존 구조에 비해 중심주파수 조절에 필요한 계수와 계수를 결정하는 커패시터의 수를 줄이고 기본적인 비중첩 클락 이외의 추가적인 클락 및 클락에 대한 부가회로가 필요하지 않다. 따라서 설계가 용이하며, 고차 구성이 가능하면서 더 높은 해상도를 가진다. $0.18{\mu}m$ CMOS 공정을 이용하여 설계하였으며, 200 kHz의 대역폭, 80 MHZ의 샘플링 주파수에서 15 MHz, 20 MHz, 25 MHz 의 중심주파수 일 때 12 bit 이상의 해상도를 가진다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.221-224
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• 2012

본 논문에서는 MEMS 가속도센서를 위한 CMOS 인터페이스 회로를 설계하였다. 설계된 CMOS 인터페이스 회로는 CVC(Capacitance to Voltage Converter), 그리고 SC-Integrator와 Comparator를 포함하는 ${\Sigma}{\Delta}$ Modulator로 구성되어 있다. 회로에 일정한 Bias를 공급할 수 있도록 Bandgap Reference를 이용하였으며, 저주파 잡음과 offset을 감소시키기 위하여 ${\Sigma}{\Delta}$ Modulator에 CHS(Chopper-Stabilization) 기법을 사용하였다. 그 결과 설계된 ${\Sigma}{\Delta}$ Modulator의 출력은 입력 전압 진폭이 100mV가 증가할 때 duty cycle은 10%의 비율로 증가하고, 전체 회로의 Sensitivity는 x, y축은 0.45V/g, z축은 0.28V/g의 결과를 얻을 수 있었다. 제안된 CMOS 인터페이스 회로는 CMOS 0.35um공정을 이용하여 설계되었다. 입력 전압은 3.3V이며, 샘플링 주파수는 2MHz이다. 설계된 칩의 크기는 PAD를 포함하여 $0.96mm{\times}0.85mm$이다.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.

• 전자공학회논문지T
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• 제35T권1호
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• pp.48-58
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• 1998

본 논문은 센서에서 수반되는 기생용량과 온도 드리프트 및 누설전류의 영향을 경감하기 위한 C-V변환회로 및 C-V변환회로에 관한 실험결과를 제시하고, 또한 논문에서 제안한 센싱 주파수를 기준주파수로 나누어줌으로써 상기 영향들을 줄일 수 있는 새로운 인터페이스 회로를 제시한다 이 회로는 용량비의 출력신호를 디지털 방식으로 16진수로 계수 함으로써 신호의 전송이나 컴퓨터 처리가 쉬울 뿐 아니라 비트수의 증가에 따라 분해 능을 향상시킬 수 있는 이점도 있다. 시작한 인터페이스 회로의 C-V 및 C-F 변환회로에서 전원전압 4.0V, 피이드백 커패시턴스10pF, 압력 0∼10 KPa범위에서 감도는 각각 28 ㎷/㎪·V, -6.6 ㎐/㎩로서 양호하였고, 온도 드리프트 특성은 0.051 %F.S./℃ 및 0.078 %F.S./℃로서 크게 개선되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.265-267
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• 2008

As generally recognized, the driving performance of a SRM at higher speed will be degraded due to the effects of back electromagnetic force (EMF). This phenomenon can be improved via voltage boosting. So in this paper an improved converter of enhancing the performance for four-phase switched reluctance motor (SRM) is proposed. By using one additional capacitor and switches, an extra controllable boosted voltage can be produced during the rise and fall periods of a motor phase current. Then this active boosted voltage can reduce the effect of EMF on the current, particularly at high speeds. The attractive features of the proposed converter are as follows: obtaining boosted voltage to improve performance of SRM with same numbers of switch and diode as asymmetric converter, having higher control flexibility and capability of boosting voltage compared with passive boosting converters, possessing lower cost and simple control in comparison with existing active boosting converters. The performances of the proposed circuit are verified by the simulation and experiment results.

• 한국컴퓨터정보학회논문지
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• 제3권2호
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• pp.77-84
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• 1998

요즈음 CMOS 기술의 발전에 의해서 연속시간 신호시스템이 매우 각광을 받고 있다. 따라서 이 논문에서는 음성신호 처리영역에서 동작하는 CMOS floating 저항을 이용한저역통과 필터를 설계하였다. 특히 이 논문에서는 포화영역에서 동작하는 all CMOS floating 저항을 설계하였으며, $\pm$1V 영역에서 $\pm$0.04%의 선형성이 얻어졌다. 주파수 응답은10MHz를 초과하였으며 능동 RC회로의 집적화에 매우 유용할것으로 생각한다. 이 방법에 의해 설계도니 저역통과필터는 SC 필터보다 그 구조가 간단하므로 IC의 형태로 만들 때 칩 면적을 많이 줄일 수 있다. 설계된 필터의 특성은 pspice에 의해 시뮬레이션 하였으며, 그 특성이 우수함이 입증되었다.

• 전력전자학회논문지
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• 제18권2호
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• pp.184-191
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• 2013

In this paper, bidirectional AC-DC converter using dual half-bridge converter is proposed. A transformer leakage inductance in the dual half-bridge converter is used for making resonance with the capacitor of the voltage-doubler, which can help the switched current to be sinusoidal without extra inductive component and also the switching loss can be reduced through operation such as ZVS, ZCS. Both circuit analysis and design guideline are described, and also the feasibility for the proposed converter is shown through the hardware implementation and the experimental results.

• Journal of Power Electronics
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• 제18권3호
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• pp.662-671
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• 2018

This paper presents a new structure for a step up dc-dc converter, which has several advantageous features. Firstly, the input dc source and the clamped capacitor are connected in series to transfer energy to the load through dual voltage multiplier cells. Therefore, the proposed converter can produce a very high voltage and a high conversion efficiency. Secondly, a double voltage clamped circuit is introduced to the primary side of the coupled inductor. The energy of the leakage inductance of the coupled inductor is recycled and the inrush current problem of the clamped circuits can be shared equally by two synchronous clamped capacitors. Therefore, the voltage spike of the switch tube is solved and the current stress of the diode is reduced. Thirdly, dual voltage multiplier cells can absorb the leakage inductance energy of the secondary side of the coupled inductor to obtain a higher efficiency. Fourthly, the active switch turns on at almost zero current and the reverse-recovery problem of the diodes is alleviated due to the leakage inductance, which further improves the conversion efficiency. The operating principles and a steady-state analysis of the continuous, discontinuous and boundary conduction modes are discussed in detail. Finally, the validity of this topology is confirmed by experimental results.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권3호
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..