• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• Journal of the Korean Society for Railway
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• v.19 no.6
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• pp.717-726
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• 2016

Emergency tracks are necessary in case a broken down train evacuates, a train needs to make way for a faster train behind it, or a train suddenly stops and following trains must avoid colliding with it. Magnetic Levitated (maglev) Trains can change track to enter an emergency track using a segmented switch or a traverse switch. On a traverse switch, a train can change its track when the part of the track that the train is on moves to the other track. Currently manufactured Maglev trains have two bodies and the total length is 25 meters. If a traverse switch is used, it will only require 30 meters of track to move the train to the other track, so, when it comes to efficiency of costs and space, the traverse switch surpasses the articulated switch. Therefore, in this paper, an optimized design to secure structural safety and weight lightening is suggested. To achieve these results, the heights of the piled concrete and girders which are both placed on the top of the traverse switch, are set as design variables. The Finite Element Method (FEM), in application of kriging and in the design of the experiments (DOE), is used. Maximum stress, deformation, and structural weight are compared with the results, and through this process structural safety and weight lightening is proven.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1673-1675
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• 2004

The design, modeling and measurement of RF switch module for GSM applications is presented in this paper. RF switch module is constructed using a LTCC multi-layer switching circuit and integrated low pass filter. Insertion and return loss of the low pass filter were designed less than 0.3 dB and better than 12.7 dB at 900 MHz. The RF switch module contained 10 embedded passives and 3 surface mount components integrated on $4.6{\times}4.8{\times}1.2$ mm, 6-layer multi-layer integrated circuit. The insertion loss of switch module was measured at 900 MHz was 11 dB.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.10-18
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• 2016

In this study, an efficient clamp is proposed to reduce the switch voltage stress of a forward converter. The proposed clamp consists of a conventional LC snubber, a tertiary winding, and a diode. When the switch is turned OFF, the magnetizing inductor energy of the transformer is recovered directly into the flyback output, which is the tertiary winding and diode network, instead of circulating in the LC snubber. Therefore, switch voltage stress and circulating current caused by the magnetizing inductor energy are reduced. This condition improves the efficiency of the forward converter with limited switch voltage stress. A theoretical analysis and the design guidelines of the proposed converter are provided. Experimental results are also reported.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.966-968
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• 2005

Generally the high-voltage and high-current making switch is used to test the short-circuit test. The making switch should be operated always same speed/time and kept electrical-mechanical characteristic. There are spring charge type, hydro-pneumatic type and compressed air type etc. according to operation method of making switch contacts. Especially the making switch contacts of hydro-pneumatic type are moved by actuator and accumulator. To keep same speed/time of contacts and characteristic of making switch, actuator and accumulator should be worked always uniformly. So the dynamic analysis of actuator and accumulator of hydro-pneumatic type making switch will be helpful to maintain and design.

• Progress in Superconductivity
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• v.5 no.1
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• pp.13-16
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• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.255-258
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• 2000

This paper presents an Interprocessor Communication Network(IPC net) in ATM switching system. In order to supply stable and independent path for processor communication, additional network i.e., Ethernet, is suggested. An Ethernet switch centered on Ethernet binds each processor into a work range. IPC net proposed in this paper assures end-to-end inter-processor connection, uniform 100Mbps Ethernet bandwidth and enhanced user cell throughput of ATM switch with minimum Ethernet supporting block integrated into ATM system

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.42-42
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• 2003