• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.10
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• pp.1137-1144
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• 2012

In this paper, a 2.6 GHz switched parasitic array(SPA) antenna is designed to resolve the device interference in the femtocell. The designed SPA antenna structure consists of a central ${\lambda}/4$ monopole antenna as a radiator and surrounding four parasitic elements operating as a reflector or a director depending on the switching state. In addition, open state monopoles around the parasitic elements are placed to improve the directivity. The designed antenna utilizes RF FETs as switching elements instead of conventional PIN diodes, which enables beam steering with a simple structure consuming low power. To select the proper FET switch, the performance of the SPA antenna depending on the switch characteristics is analyzed. The fabricated antenna has 65 mm radius and 35 mm height, which shows about 15 dB front-back-ratio(FBR) at 2.6 GHz and enables eight-directional beam steering.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.136-144
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• 2010

This paper presents the two-switch interleaved active clamp forward converter, which is mainly composed of two active clamp forward converters. Only two switches are required, and each one is the auxiliary switch for the other. So, the circuit complexity and cost are reduced and control is more simple. An additional resonant inductance is employed to achieve ZVS(Zero-Voltage-Switching) during the dead times. Interleaved output inductor currents diminish the voltage and current ripple. Accordingly, the smaller output filter and capacitors lower the converter volume. This research proposed the Two-switch interleaved Active Clamp Forward Converter characteristic. The principle of operation, feature and design considerations is illustrated and the validity of verified through the experiment with a 160[W] based experimental circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.732-741
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• 2018

In order to maximize the usable capacity of a BMS (battery management system) that uses several battery cells connected in series, a cell balancing technique that equips each cell with the same voltage is needed. In the active cell balancing circuit using a multi-winding transformer, a balancing circuit that transfers energy directly to the cell (cell-to-cell) is composed of a PMOS switch and a gate driving chip for driving the NMOS switch. The TLP2748 photocoupler and the TLP2745 photocoupler are required, resulting in increased cost and reduced integration. In this paper, instead of driving PMOS and NMOS switching devices by using photocoupler, we proposed 70V BCD process based PMOS gate driving circuit, NMOS gate driving circuit, PMOS gate driving circuit and NMOS gate driving circuit with improved switching time. ${\Delta}t$ of the PMOS gate drive switch with improved switching time was 8.9 ns and ${\Delta}t$ of the NMOS gate drive switch was 9.9 ns.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.333-333
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• 2004

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.1-11
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• 1999

It is now common practice to utilize the quadrature RF coils to improve the signal-to-noise ratio (SNR) in the Magnetic Resonance Imaging (MRI) System. In addition, to make such an available SNR improvement, it is mandatory to use a well-designed quadrature coupler, which facilitates a perfect 3-dB coupling and quadrature-phase shift. However, the four ports matching condition has to be well considered during the RF excitation and the signal detection period. This work investigates the effects of such a mismatching condition (especially, due to patient) from the analysis, simulation, and real implementation and firstly proposes dynamic loading technique for a quadrature coupler and transmitting/receiving switch module to minimize a patient mismatching and enhance a system reliability. Also, we designed and implemented the quadrature coupler and transmitting/receiving switch module using microstrip. As a result, the SNR of our MRI system using the microstrip quadrature coupler and transmitting/receiving switch module with dynamic load increases 3 dB compared with the old one using USA quadrature switch. Also, the power capability of quadrature coupler and transmitting/receiving switch module is 5-kw peak power. Considering power loss and reduction of size, we used a RT/duroid 6010 substrate with high permittivity and for simulation we use Compact Software.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• ETRI Journal
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• v.38 no.4
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• pp.654-664
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• 2016

This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.155-159
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• 2004

This paper describes the design and the simulation of a single pole double throw(SPDT) FET switch for wireless LAN(IEEE802.11a ＆ IEEE802.11b) applications using drain impedance transformation network with Microstrip transmission line. At the receiving path insertion losses were from 0.8(㏈) to 1.462(㏈) between 2(㎓) and 4(㎓), from l.26(㏈) to 2.3(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓). At the transmitting path insertion loss were from 1.18(㏈) to 2.87(㏈) between 2(㎓) and 4(㎓) from 0.625(㏈) to 1.2(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓).