• Proceedings of the KSR Conference
• /
• 2002.10b
• /
• pp.995-1000
• /
• 2002

This paper presents general concept of DC switch gear(DCSWGR). Normally, DCSWGR consist of Digital protection unit(DPU), High Speed Circuit Breaker(HSCB), Disconnect Switch (DS), Programmable Logic Control(PLC), Auxiliary Relays and etc. Most of the components has its special characteristics and their interface between each others are various and complex. In this paper every constituent general design are preceded and interface between each component are examined. And also DCSWGR operation logic with logical diagram including interlock signal are introduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.425-429
• /
• 2002

In this paper, a single-phase inverter using a diode bridge-type resonant circuit to implement ZVT(Zero Voltage Transition) switching is presented. The current control algorithm is analyzed about how to design the circuit with auxiliary switch which can ZVT operation for the main power switch. The simulation and experimental results would be shown to verify the proposed current algorithm, because the main power switch is turn on with ZVT and the hi-directional inverter is operated.

• Proceedings of the KIEE Conference
• /
• 2000.07b
• /
• pp.1292-1295
• /
• 2000

In this paper, we proposed a new single-stage single-switch power factor correction(S-4 PFC) converter with output electrical isolation. The configuration of this converter is achieved by combining a fly back circuit and a forward circuit in one power stage. To verify the theoretical analysis of the proposed converter, a design example is given with its Pspice simu-lation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.812-822
• /
• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.38 no.11
• /
• pp.1309-1315
• /
• 2014

The switch for a maglev vehicle should be designed such that the vehicle safely changes its track without touching the guiderail. In particular, a medium-to-low-speed EMS -type maglev train relies heavily on a U-type electromagnet where it generates levitation force and guidance force simultaneously. Therefore, it is necessary to evaluate the safety of the vehicle whenever it passes the switch, as it lacks active control of the guidance force. Furthermore, when the vehicle passes a segmented switch, which is a group of curves made up of connected lines with a small radius of curvature, it may come into mechanical contact with the guiderail owing to the excessive lateral displacement of the electromagnet. The goal of this study is to analyze the influence of a segmented switch on the safety of major design-related variables for achieving improved running safety. We propose a three-dimensional multibody dynamics model composed of two cars with one body. Using the proposed model, we perform a simulation of the lateral air gap, which is one of the measurements of the running safety of the vehicle when it passes the switch. The analyzed design variables are the length between short span girder, the articulation angle, the length between two centers of a fixed girder at its ends, and the number of girders. On the basis of the effects of the considered design variables, we establish an optimized design of a switch with improved safety.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.3
• /
• pp.82-88
• /
• 2015

This paper presents a design of the enable switch circuit, which is consist of discrete device at smart junction box(SJB) board. The Enable switch circuit, which receives ignition signal (IG) for input, sends a drive signal to linear regulator and other elements. The circuit design is carried out in a BCDMOS $0.18{\mu}m$ technology, and the performances are verified through simulations according to AEC-Q100 and ISO 7637-2. Die area of the designed Enable switch circuit is $1.67mm{\times}0.54mm$ in layout, and it is shown that the die can be housed in $3mm{\times}3mm$ HVSON8 package. The designed enable switch circuit is expected to be widely adopted in various automotive SJB's since it can significantly reduce the overall printed circuit board form factor.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.5
• /
• pp.35-41
• /
• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.17 no.7
• /
• pp.1823-1840
• /
• 2023

In order to improve spectral efficiency and reduce power consumption for reconfigurable intelligent surface (RIS) assisted wireless communication systems, a joint design considering irregular RIS topology, RIS on-off switch, power allocation and phase adjustment is investigated in this paper. Firstly, a multi-dimensional variable joint optimization problem is established under multiple constraints, such as the minimum data requirement and power constraints, with the goal of maximizing the system energy efficiency. However, the proposed optimization problem is hard to be resolved due to its property of nonlinear nonconvex integer programming. Then, to tackle this issue, the problem is decomposed into four sub-problems: topology design, phase shift adjustment, power allocation and switch selection. In terms of topology design, Tabu search algorithm is introduced to select the components that play the main role. For RIS switch selection, greedy algorithm is used to turn off the RISs that play the secondary role. Finally, an iterative optimization algorithm with high data-rate and low power consumption is proposed. The simulation results show that the performance of the irregular RIS aided system with topology design and RIS selection is better than that of the fixed topology and the fix number of RISs. In addition, the proposed joint optimization algorithm can effectively improve the data rate and energy efficiency by changing the propagation environment.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2001.02a
• /
• pp.114-116
• /
• 2001

This paper deals with the design and fabrication of loop superconducting Persistent Current Switch(PCS) circuit. The self and mutual inductances of the circuits are calculated and compared to the measured values. The size of loop circuits was determined using the calculated inductances, and the fabrication processes of the superconducting persistent current switch are described.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.05a
• /
• pp.479-480
• /
• 2012