• 한국재료학회지
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• 제10권9호
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• pp.593-600
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• 2000

본 연구에서는 도핑하지 않은 다이아몬드 박막에서의 전류전도 경로를 체계적으로 규명하고 다이아몬드 박막의 전도기구에 대해 조사하였다. 도핑되지 않은 다결정 다이아몬드 박막에서 두께와 측정방향에 따른 교류 임피던스법에 의해 측정된 저향값이 기존의 표면전도 모델과는 일치하지 안니하였다. 다이아몬드 박막에 구리를 전기도금한 결과 구리는 결정립계에만 불연속적으로 도금되었고 다이아몬드 박막 위에 은을 증착한 후 전지에칭을 한 결과 결정립계가 우선 에칭이 되어 전류가 결정립계를 통하여 흐름을 확인하였다. 또, 리본형 다이아몬드 박막의 표면을 절연층으로 형성시킨 후 박막 내부의 결정립계를 통하여 전류가 흘러 전기도금이 되는 것으로부터 다결정 다이아몬드 박막의 주요 전기전도 경로는 결정립계임을 확인하였다. 높은 전기전도도를 보여주는 다이아몬드 박막은 전도 활성화 에너지가 45meV 정도이었고 dangling bond 밀도는 낮았다. 그러나 산소 열처리나 수소플라즈마처리가 Si passivation 이론과는 반대로 dangling bond 밀도를 증가시키면서 전기전도성을 떨어뜨렸다. 이 결과들과 표면의 탄소화학결합을 연결시켜 높은 전도성을 야기시키는 결합은 H-C-C-H 결합임을 추론하였다.

• Tribology and Lubricants
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• 제31권3호
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• pp.79-85
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• 2015

RC delay is a critical issue for achieving high performance of ULSI devices. In order to minimize the RC delay time, we uses the CMP process to introduce high-conductivity Cu and low-k materials on the damascene. The low-k materials are generally soft and fragile, resulting in structure collapse during the conventional high-pressure CMP process. One troubleshooting method is electrochemical mechanical polishing (ECMP) which has the advantages of high removal rate, and low polishing pressure, resulting in a well-polished surface because of high removal rate, low polishing pressure, and well-polished surface, due to the electrochemical acceleration of the copper dissolution. This study analyzes an electrochemical state (active, passive, transpassive state) on a potentiodynamic curve using a three-electrode cell consisting of a working electrode (WE), counter electrode (CE), and reference electrode (RE) in a potentiostat to verify an electrochemical removal mechanism. This study also tries to find optimum conditions for ECMP through experimentation. Furthermore, during the low-pressure ECMP process, we investigate the effect of current density on surface roughness and removal rate through anodic oxidation, dissolution, and reaction with a chelating agent. In addition, according to the Faraday’s law, as the current density increases, the amount of oxidized and dissolved copper increases. Finally, we confirm that the surface roughness improves with polishing time, and the current decreases in this process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.457-457
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• 2010

Flexible organic light emitting diodes (F-OLEDs) requires excellent moisture permeation barriers to minimize the degradation of the F-OLEDs device. Specifically, F-OLEDs device need a barrier layer that transmits less than $10^{-6}g/m^2/day$ of water and $10^{-5}g/m^2/day$ of oxygen. To increase the life time of F-OLEDs, therefore, it is indispensable to protect the organic materials from water and oxygen. Severe groups have reported on multi-layerd barriers consisting inorganic thin films deposited by plasma enhenced chemical deposition (PECVD) or sputtering. However, it is difficult to control the formation of granular-type morphology and microscopic pinholes in PECVD and sputtering. On the contrary, atomic layer deoposition (ALD) is free of pinhole, highly uniform, conformal films and show good step coverage. Thus, $Al_2O_3/TiO_2$ multi-layer was deposited onto the polyethersulfon (PES) substrate by electron cyclotron resonance atomic layer deposition (ECR-ALD), and the water vapor transmission rates (WVTR) were measured. WVTR of moisture permeation barriers is dependent upon density of films and initial state of polymer surface. A significant reduction of WVTR was achieved by increasing density of films and by applying low plasma induced interlayer on the PES substrate. In order to minimize damage of polymer surface, a 10 nm thick $TiO_2$ was deposited on PES prior to a $Al_2O_3$ ECR-ALD process. High quality barriers were developed from $Al_2O_3$ barriers on the $TiO_2$ interlayer. WVTR of $Al_2O_3$ by introducing $TiO_2$ interlayer was recorded in the range of $10^{-3}g/m^2.day$ at $38^{\circ}C$ and 100% relative humidity using a MOCON instrument. The WVTR was two orders of magnitude smaller than $Al_2O_3$ barriers directly grown on PES substrate without the $TiO_2$ interlayer. Thus, we can consider that the $Al_2O_3/TiO_2$ multi-layer passivation can be one of the most suitable F-OLEDs passivation films.

• 한국진공학회지
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• 제5권3호
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• pp.239-244
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• 1996

비정질 Si 막의 증착을 위해 승온시 $Si_2H_6$ 가스를 주입함으로써 Si 표면의 $SiO_2$ 의 형성을 방지할 수 있었다. 또한 이렇나 공정을 이용하여 증착된 비정질 Si 의 후열처리에 의한 고상 에피텍시 성장이 가능하였다. 승온시 $Si_2H_6$ 가스 주입에 의한 표면 $SiO_2$의 형성 방지는 증착 승온시 SiHx 분위기를 만들어 줌으로써 , Si 기판표면의 passivation H의 탈착과 동시에 일어나는 반응기 잔류 가스중에 의한 O의 흡착대신 SiHx를 흡착시킴으로써 가능한 것으로 판단된다. 이러한 방법을 이용하여 기존에 보고된 고온 cleaning 공정없이도 고품위의 결정성을 갖는 에피텍시 막을 $600^{\circ}C$미만의 저온 공정으로 제조할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1996년도 제11회 학술발표회 논문개요집
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• pp.40-41
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• 1996

Nitridation technique has been receiving much attention for the formation of a thin nitrided buffer layer on which high quality nitride films can be formedl. Particularly, gallium nitride (GaN) has been considered as a promising material for blue-and ultraviolet-emitting devices. It can also be used for in situ formed and stable passivation layers for selective growth of $GaAs_2$. In this work, formation of a thin nitrided layer is investigated. Nitrogen electron cyclotron resonance(ECR)-plasma is employed for the formation of thin nitrided layer. The plasma source used in this work is a compact ECR plasma gun3 which is specifically designed to enhance control, and to provide in-situ monitoring of plasma parameters during plasma-assisted processing. Microwave power of 100-200 W was used to excite the plasma which was emitted from an orifice of 25 rnm in diameter. The substrate were positioned 15 em away from the orifice of plasma source. Prior to nitridation is performed, the surface of n-type (001)GaAs was exposed to hydrogen plasma for 20 min at $300{\;}^{\circ}C$ in order to eliminate a native oxide formed on GaAs surface. Change from ring to streak in RHEED pattern can be obtained through the irradiation of hydrogen plasma, indicating a clean surface. Nitridation was carried out for 5-40 min at $RT-600{\;}^{\circ}C$ in a ECR plasma-assisted molecular beam epitaxy system. Typical chamber pressure was $7.5{\times}lO^{-4}$ Torr during the nitridations at $N_2$ flow rate of 10 seem.(omitted)mitted)

• 한국표면공학회지
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• 제31권1호
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• pp.54-62
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• 1998

In this study, the behaviorof ion nitriding of AISI 304 stainless steel was investigated using plasma ion nitriding system. The characteristics of ion nitriding, and their micsoctrucyures, and physical properties were investigated as a function of process parmeteds. important conclusions can be summarzied as follows. Firstly, it was found that growth of nitride layer in ion nitriding are mainly affected by N2 partial pressures and nitriding temperatures for AISI 304 stainless steel. The $N_2$<\TEX> partial pressure plays on important role in ion nitriding since it determiness the incoming flux of nitrogen species onto specimen surface. Nitriding thmprrature is also important besauseit determines the diffusion rates of nitrogen through nitride layers. While both parameters affects the characteristics rateding are controlled by nitridingen diffusion nitration profiles of N and alloying elements such as Cr and Ni are observed through niride layers. Secondly, nitride layer consists of the upper white laywe having various nitride phases and the underneath diffusion layers. The thickness of white layer increases with $N_2$<\TEX> partial pressures and nitriding temperatures. The thinkness of diffusion layer is increasting nitriding temperatures. Finally, nitriding of stainless steels steel show slighly low their corrsionce prorerties. However, passivation properties, which is normally observed in stainless steels, were still observed aftre ion nitriding.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.55-55
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• 2018

Recently, amorphous oxides such as InGaZnO (IGZO) and InZnO (IZO) as a channel layer of an oxide TFT have been attracted by advantages such as high mobility, good uniformity, and high transparency. In order to apply such an amorphous oxide TFTs to a display, the stability in various environments must be ensured. In the InGaZnO which has been studied in the past, Ga elements act as a suppressor of oxygen vacancy and result in a decreased mobility at the same time. Previous studies have been showed that the InZnO, which does not contain Ga, can achieve high mobility, but has relatively poor stability under various instability environments. In this study, the TFTs using $IZO/Al_2O_3$ double layer structure were studied. The introduction of an $Al_2O_3$ interlayer between source/drain and channel causes superior electrical characteristics and electrical stability as well as reduced contact resistance with optimally perfect ohmic contact. For the IZO and $Al_2O_3$ bilayer structures, the IZO 30nm IZO channels were prepared at $Ar:O_2=30:1$ by sputtering and the $Al_2O_3$ interlayer were depostied with various thickness by ALD at $150^{\circ}C$. The optimal sample exhibits considerably good TFT performance with $V_{th}$ of -3.3V and field effect mobility of $19.25cm^2/Vs$, and reduced $V_{th}$ shift under positive bias stress stability, compared to conventional IZO TFT. The enhanced TFT performances are closely related to the nice ohmic contact properties coming from the defect passivation of the IZO surface inducing charge traps, and we will provide the detail mechanism and model via electrical analysis and transmission line method.

• 한국재료학회지
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• 제18권12호
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• pp.640-644
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• 2008

ZnO/ZnS core/shell nanocrystals (${\sim}5-7\;nm$ in diameter) with a size close to the quantum confinement regime were successfully synthesized using polyol and thermolysis. X-ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM) analyses reveal that they exist in a highly crystalline wurtzite structure. The ZnO/ZnS nanocrystals show significantly enhanced UV-light emission (${\sim}384\;nm$) due to effective surface passivation of the ZnO core, whereas the emission of green light (${\sim}550\;nm$) was almost negligible. They also showed slight photoluminescence (PL) red-shift, which is possibly due to further growth of the ZnO core and/or the extension of the electron wave function to the shell. The ZnO/ZnS core/shell nanocrystals demonstrate strong potential for use as low-cost UV-light emitting devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.347.2-347.2
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• 2016

Recently, in order to improve the performance of the colloidal quantum dot solar cells (CQDSCs), various efforts such as the modification of the cell architecture and surface treatment for quantum dot (QD) passivation have been made. Especially, the incorporation of halides into the QD matrix was reported to improve the performances significantly via passivating QD trap states that lower the life-time of the minority-carrier. In this work, we fabricated a lead sulfide (PbS) QD bilayer treated with different ligands and utilized it as a photoactive layer of the CQDSCs. The bottom and top PbS layer was treated using metal iodide ($MI_x$ and butanedithiol (BuDT), respectively. All the depositions and ligand treatments were carried out in air using layer-by-layer spin-coating process. The fabrication of the active layers as well as the n-type zinc oxide (ZnO) layer was successfully carried out on the bendable indium-tin-oxide (ITO)-coated polyethylene terephthalate (PET) substrate, which implies that this technique can be applied to the fabrication of flexible and/or wearable solar cells. The power conversion efficiency (PCE) of the CQDSCs with the architecture of $PET/ITO/ZnO/PbS-MI_x/PbS-BuDT/MoO_x/Ag$ reached 4.2 %, which is significantly larger than that of the cells with single QD (PbS-BuDT) layer.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.