• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1443-1449
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• 2009

This paper presents a profiling model of a wide-window superscalar microprocessor using multiple branch prediction. The key idea is to apply statistical profiling technique to the superscalar microprocessor with a wide instruction window and a multiple branch predictor. The statistical profiling data are used to obtain a synthetical instruction trace, and the consecutive multiple branch prediction rates are utilized for running trace-driven simulation on the synthesized instruction trace. We describe our design and evaluate it with the SPEC 2000 integer benchmarks. Our performance model can achieve accuracy of 8.5 % on the average.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.423-428
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• 2010

In the initial design phase of superscalar microprocessors, a performance model is necessary. A theoretic performance model is very useful since performance for various architecture parameters can be obtained by simply computing equations, without repeating simulations, Previous studies established theoretic performance models using the relation between the instruction window size and the issue width, with the penalties due to branch mispredictions and cache misses. However, the study was intended for unlimited number of functional units, which is insufficient for the real case application. This paper proposes a superscalar microprocessor theoretical performance model which also works for the limited functional units. To enhance the accuracy of our limited functional unit model, instruction dependency rates are employed. By using trace-driven data of SPEC 2000 integer programs as input, this paper shows that the theoretically computed performance of superscalar microprocessor with limited number of functional units is quite similar to the measured performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• ETRI Journal
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• v.22 no.4
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.558-566
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• 2000

Object recognition is a challenging application for high-performance computing. Currently, the superscalar architecture dominates todays microprocessor marketplace. As more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the object recognition on the on-chip multiprocessor, which will be employed in general-purpose parallel machines. To obtain the performance characteristics of the microprocessor, a program-driven simulator and its programming environment were developed. The simulation results showed that the on-chip multiprocessor can exploit thread level parallelisms effectively and offer a promising architecture for the object recognition application.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.297-305
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• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.3-12
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• 2001

Currently, the superscalar architecture dominates todays microprocessor marketplase. As, more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the next generation block encryption algorithms RC6 and Rijndael on the on-chip multiprocessing microprocessor. Based on the simulation results by using a program-driven simulator, the on-chip multiprocessor can exploit thread level parallelism effectively and overcome the limitation of instruction level parallelism in the next generation block encryption algorithms.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1153-1156
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• 1998

We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.