• 제목/요약/키워드: Summation circuit

검색결과 15건 처리시간 0.023초

고출력 18650 리튬이온 배터리의 발열인자 해석 및 실험적 검증 (Analysis and Experiment Verification of Heat Generation Factor of High Power 18650 Lithium-ion Cell)

  • 강태우;유기수;김종훈
    • 전력전자학회논문지
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    • 제24권5호
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    • pp.365-371
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    • 2019
  • This study shows the feasibility of the parameter of the 1st RC parallel equivalent circuit as a factor of the heat generation of lithium-ion cell. The internal resistance of a lithium-ion cell consists of ohmic and polarization resistances. The internal resistances at various SOCs of the lithium-ion cell are obtained via an electrical characteristic test. The internal resistance is inversely obtained through the amount of heat generated during the experiment. By comparing the resistances obtained using the two methods, the summation of ohmic and polarization resistances is identified as the heating factor of lithium-ion battery. Finally, the amounts of heat generated from the 2C, 3C, and 4C-rate discharge experiments and the COMSOL multiphysics simulation using the summation of ohmic and polarization resistances as the heating parameter are compared. The comparison shows the feasibility of the electrical parameters of the 1st RC parallel equivalent circuit as the heating factor.

CMOS Synaptic Model Considering Spatio-Temporal Summation of lnputs

  • Fujita, Takeshi;Matsuoka, Jun;Saeki, Katsutoshi;Sekine, Yoshifumi
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -2
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    • pp.1188-1191
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    • 2002
  • A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.

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Integrate-and-Fire Neuron Circuit and Synaptic Device using Floating Body MOSFET with Spike Timing-Dependent Plasticity

  • Kwon, Min-Woo;Kim, Hyungjin;Park, Jungjin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권6호
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    • pp.658-663
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    • 2015
  • In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

철손을 고려한 단상 영구자석형 유도동기기의 특성해석 (Characteristic Analysis of Single-phase Line-start Permanent Magnet Synchronous Motor Considering Iron Loss)

  • 남혁;강규홍;홍정표
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제53권5호
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    • pp.295-304
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    • 2004
  • This paper deals with characteristic analysis method using d-q axis equivalent circuit considering iron loss in a single-phase line-start permanent magnet synchronous motor. The iron loss resistance to account for the iron loss is included in the equivalent circuit to improve the modeling accuracy. Furthermore, for the improved calculation of the iron loss, the iron loss is calculated from the magnetic flux density by 2-dimensional finite element method. The result is represented as the iron loss resistance and connected in parallel with the total induced voltage. Therefore, the currents can be expressed as the summation the output current with the current corresponding to the iron loss. Finally, the steady state characteristic analysis results are compared with the experimental results to verify this approach.

신경세포의 전기적 모델화 (A study of the electrical neuronal model)

  • 박상희;이명호
    • 전기의세계
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    • 제24권6호
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    • pp.97-101
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    • 1975
  • The electrical neuronal model described in this paper simulates the most important functional properties of nerve cells. An model circuit incorporating many of the digital and analog properties of neurons is described. Having such properties as variable threshold level, action potential, summation, all-or-none output, absolute and relative refract oriness, and ingibition, it exhibits a considerable amount of functional equivalence to biological structures. This electrical neuronal model has utility not only for studying single unit properties but also for investigating group interactions. Such studies may be relevent to elucidation of neuronal network behavior.

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Leakage Current Energy Harvesting Application in a Photovoltaic (PV) Panel Transformerless Inverter System

  • Khan, Md. Noman Habib;Khan, Sheroz
    • Transactions on Electrical and Electronic Materials
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    • 제18권4호
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    • pp.190-194
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    • 2017
  • Present-day solar panels incorporate inverters as their core components. Switching devices driven by specialized power controllers are operated in a transformerless inverter topology. However, some challenges associated with this configuration include the absence of isolation, causing leakage currents to flow through various components toward ground. This inevitably causes power losses, often being also the primary reason for the power inverters' analog equipment failure. In this paper, various aspects of the leakage currents are studied using different circuit analysis methods. The primary objective is to convert the leakage current energy into a usable DC voltage source. The research is focused on harvesting the leakage currents for producing circa 1.1 V, derived from recently developed rectifier circuits, and driving a $200{\Omega}$ load with a power in the milliwatt range. Even though the output voltage level is low, the harvested power could be used for charging small batteries or capacitors, even driving light loads.

장애물이 있는 작업공간에서 신경최적화 회로망에 의한 다중 이동로봇트의 경로제어 (Collision-Free Trajectory Control for Multiple Mobile Robots in Obstacle-resident Workspace Based on Neural Optimization Networks)

  • 이지홍
    • 대한전기학회논문지
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    • 제39권4호
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    • pp.403-413
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    • 1990
  • A collision free trajectory control for multiple mobile robots in obstacle-resident workspace is proposed. The proposed method is based on the concept of neural optimization network which has been applied to such problems which are too complex to be handled by traditional analytical methods, and gives good adaptibility for unpredictable environment. In this paper, the positions of the mobile robot are taken as the variables of the neural circuit and the differential equations are derived based on the performance index which is the weighted summation of the functions of the distances between the goal and current position of each robot, between each pair of robots and between the goal and current position of each robot, between each pair of robots and between obstacles and robots. Also is studied the problem of local minimum and of detour in large radius around obstacles, which is caused by inertia of mobile robots. To show the validity of the proposed method an example is illustrated by computer simulation, in which 6 mobile robots with mass and friction traverse in a workspace with 6 obstacles.

2안정 멀티바이브레이터 터널 다이오우드 대회로의 해석 (Analysis of a Two Stable Multi-Vibrator using a Tunnel Diode Pair Circuit)

  • 이광형
    • 한국통신학회논문지
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    • 제8권1호
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    • pp.38-42
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    • 1983
  • 1개의 터널 다이오우드(TD)의 稱特性을 커어브 트레서로부터 2개의 指數項을 합으로 나타내어 電子計算機에 의해 TC對特性을 플롯한 결과 理論値의 2%이내의 오차로 近似시킬 수 있었다. 이와 같이 구한 對特性을 이용하여 MV(멀티바이브레이터)트리거作動을 形式的으로 잘 說明할 수 있었으며 安定特性을 區間直線法에 의해서 解析한 結果는 實驗値와 잘 일치함을 알았다.

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연산증폭기와 온도보상 다이오드에 의한 D-A 변환기의 특성개선 (On Improvement of D-A Converter)

  • 이희두;안수길
    • 대한전자공학회논문지
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    • 제7권2호
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    • pp.21-25
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    • 1970
  • 같은 특성의 다이오드를 스위칭 용과 기준 전원 온도보상에 사용하여 온도특성을 개선한 디지탈-아나로그변환기를 연구하였다. 연산 증폭기를 사용함으로써 가산용 체형회로망을 제거금하고 담선된 직선성을 얻었다. Slewing rate 증가를 꾀하여 1.5 mega bit 속도의 디지트 정보를 수신하여 출력전과의 안정된 신호부분이 전주간의 80% 이상 특매도록 하였다.

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계층적인 구조를 갖는 고속 병렬 곱셈기 (A High Speed Parallel Multiplier with Hierarchical Architecture)

  • 진용선;정정화
    • 대한전자공학회논문지TE
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    • 제37권3호
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    • pp.6-15
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    • 2000
  • 본 논문에서는 고속 4-2 compressor와 6-2 compressor 를 사용한 계층적인 구조를 갖는 병렬 곱셈기를 제안한다. 병렬곱셈기는 일반적으로 CSA 덧셈기를 사용한 부분곱 덧셈 트리 블록의 처리속도에 영향을 받는다. 따라서, 본 논문에서는 일반적인 CSA 덧셈기 회로보다 전달 지연시간을 감소시킨 고속 4-2 compressor와 6-2 compressor 회로를 제안한다. 또한, 제안하는 compressor를 사용하여 16×16 병렬곱셈기의 처리속도를 향상시키며 규칙적인 레이아웃을 할 수 있는 계층적 곱셈기 구조를 제안한다. 제안하는 4-2 compressor 회로를 SPICE 시뮬레이션 한 결과 기존의 4-2 compressor 회로에 비하여 전달지연 시간을 14% 감소시킬 수 있었다. 한편 제안하는 4-2 compressor와 6-2 compressor를 사용하여 16×16 비트 병렬곱셈기를 설계한 결과 일반 병렬곱셈기에 비하여 총 전달지연시간이 12% 이상 감소되었다

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