• Title/Summary/Keyword: Successive Approximation

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APPLICATION OF BENFOR'S EQUATIONS TO THE PROBLEM OF "SEEING THROUGH LAYERS"

  • Krivoshiev, Georgi -P.;Chalucova, Raina-P.;Dahm, Donald-J.
    • Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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    • 2001.06a
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    • pp.1132-1132
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    • 2001
  • This work is a further development of the method created by G. Krivoshiev in 1996 for elimination of peel interference and prediction of fruit flesh optical density. In this investigation, as it was earlier, the objects are observed as being structured by three successive layer “AlongrightarrowOlongrightarrowB” denoting “peel-flesh-peel”. In the first version of the method the transmittances of the surface layers A and B were measured according to Kubelka-Munk theory by means of their diffuse reflectance. At that the overall transmittance T was approximated in the form of a multiplication approximation being valid for plane-parallel layers of a non-scattering material. In this work this approximation was done away with applying the theory of discontinuum, respectively Benfor's equations. As a result two mathematical models were created for non-destructive prediction of fruit flesh optical density. These models are different from the ones based solely on Kubelka-Munk theory, the destruction being marked by the terms 1n (1 - $R_{A}R_{0}$) and 1n (1 - $R_{A}R_{B}$), where: $R_{A}$ and $R_{B}$ are reflectance values for the surface layers A and B; $R_{0}$ is the average reflectance of the internal layer that could be obtained empirically by means of a preliminary measurement of sufficiently large number of physically peeled fruits of a given species and variety.

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Optimal Control by the Gradient Method (경사법에의한 최적제어)

  • 양흥석;황희융
    • 전기의세계
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    • v.21 no.3
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    • pp.48-52
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    • 1972
  • The application of pontryagin's Maximum Principle to the optimal control eventually leads to the problem of solving the two point boundary value problem. Most of problems have been related to their own special factors, therfore it is very hard to recommend the best method of deriving their optimal solution among various methods, such as iterative Runge Kutta, analog computer, gradient method, finite difference and successive approximation by piece-wise linearization. The gradient method has been applied to the optimal control of two point boundary value problem in the power systems. The most important thing is to set up some objective function of which the initial value is the function of terminal point. The next procedure is to find out any global minimum value from the objective function which is approaching the zero by means of gradient projection. The algorithm required for this approach in the relevant differential equations by use of the Runge Kutta Method for the computation has been established. The usefulness of this approach is also verified by solving some examples in the paper.

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NUMERICAL SIMULATION OF PLASTIC FLOW BY FINITE ELEMENT LIMIT ANALYSIS

  • Hoon-Huh;Yang, Wei-H.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 1992.03a
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    • pp.159-176
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    • 1992
  • Limit analysis has been rendered versatile in many problems such as structural problems and metal forming problems. In metal forming analysis, a slip-line method and an upper bound method approach to limit solutions is considered as the most challenging areas. In the present work, a general algorithm for limit solutions of plastic flow is developed with the use of finite element limit analysis. The algorithm deals with a generalized Holder inequality, a duality theorem, and a combined smoothing and successive approximation in addition to a general procedure for finite element analysis. The algorithm is robust such that from any initial trial solution, the first iteration falls into a convex set which contains the exact solution(s) of the problem. The idea of the algorithm for limit solution is extended from rigid/perfectly-plastic materials to work-hardening materials by the nature of the limit formulation, which is also robust with numerically stable convergence and highly efficient computing time.

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Optimization of Process Parameters for Mill Scale Recycling Using Taguchi Method (다구찌 방법을 이용한 밀스케일 재활용에 대한 공정변수의 최적화)

  • Baek, Seok-Heum;Joo, Won-Sik;Kim, Chang-Kee;Jeong, Yu-Yeob;Shin, Shang-Woon;Hong, Soon-Hyeok
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.2
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    • pp.88-95
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    • 2008
  • With society focusing more and more on environmental issues, the recycling of materials of all types has become an important concern. In this paper, optimization method is developed for reducing cost and improving quality in mill scale recycling. An experimental investigation into the process parameter effects is presented to determine the optimum configuration of parameters for performance, quality and cost. Taguchi's optimization approach was used to obtain the optimal parameters. The significant parameters were identified and their effects on mill scale recycling were studied. As a results, a confirmation experiment with the optimal levels of process parameters was carried out in order to demonstrate the effectiveness of the Taguchi method.

A 8-bit 10-MHz CMOS A/D Converter (8-bit 10-MHz CMOS A/D 변환기)

  • 박창선;손주호;이준호;김종민;김동용
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.263-266
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    • 1999
  • In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

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Embedded Zero-tree Wavelet (EZW) Image Compression Using Multi-Threshold (다중 임계값을 이용한 임베디드 제로트리 웨이블렛(EZW) 영상압축)

  • 방민기;조창호;이상효;박종우;이종용
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2311-2314
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    • 2003
  • In this paper, the embedded zero-tree wavelet image compression method using multi- threshold is proposed, which can reduce the scanning and symbol redundancy of the existing embedded zero-tree wavelet (EZW) method and enable more efficient coding. In the proposed scheme, a multi-threshold is constructed with the maximum absolute values from each subband decomposed by the wavelet transforms of the input image data. The multi-threshold values are compared with the threshold value T$_1$ in each pass in Successive Approximation Quantization (SAQ) to select the significant subbands, which are only used for the subsequent coding processes, therefore, can reduce the coding redundancy in the existing EZW. By the experimental results, it is verified that the proposed multi-threshold EZW method shows superior performances to the existing EZW method.

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Robust $H_{\infty}$ Control for Bilinear Systems via State Feedback (상태 피드백에 의한 쌍일차 계통의 강인 $H_{\infty}$ 제어)

  • Kim, Young-Joong;Kim, Beom-Soo;Lim, Myo-Taeg
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2037-2039
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    • 2002
  • This paper focuses on robust $H_{\infty}$ control for bilinear systems with time-varying parameter uncertainties via state feedback. The suitable robustly stabilizing feedback control law can be constructed in term of solution to a state variable x-dependent quadratic Riccati equation using successive approximation technique. Also, the state feedback control law robustly stabilizes the plant and guarantees a robust $H_{\infty}$ performance for the closed-loop bilinear system with parameter uncertainties and exogenous disturbance.

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A High-Resolution Dual-Loop Digital DLL

  • Kim, Jongsun;Han, Sang-woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.520-527
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    • 2016
  • A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

A Study on the Noise Characteristics for the PCM-FSK Communication Systems (PCM-FSK 통신의 잡음특성에 관한 연구)

  • 신철재;김용득
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.15 no.5
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    • pp.7-12
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    • 1978
  • The successive-approximation analog-to digital conversion has been rosed to design the FSK Communication systems. The mathematical Boise is computed under the worst condition and the improved method of the FSK is suggested in the field of the real communication systems. The measured results show that the signal to noise ratio is more than 27dB, and it gives a good agreement with the mathematical analysis.

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A 12-bit 1MSps SAR ADC using MOS Capacitor (MOS 커패시터를 이용한 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기)

  • Seong, Myeong-U;Kim, Cheol-Hwan;Choi, Seong-Kyu;Choi, Geun-Ho;Kim, Shin-Gon;Han, Gi-Jung;Rastegar, Habib;Ryu, Jee-Youl;Noh, Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.293-294
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    • 2014
  • 본 논문에서는 MOS 커패시터를 이용하여 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 매그나칩/SK하이닉스 $0.18{\mu}m$ 공정을 이용하였으며, Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 3.22mW였고, 유효 비트수는 11.5bit의 결과를 보였다.

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