• 한국초전도학회:학술대회논문집
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• v.13
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• pp.21-21
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• 2003

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.335-336
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• 2009

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.867-870
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• 1998

In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.51-58
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• 1995

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.168-169
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• 2002

Magnetic tunneling junction을 이용한 MRAM의 실용화에 있어서 무엇보다 중요한 요소 중의 하나는 밀도를 높이는 것으로, MRAM이 경쟁력을 갖는 메모리 소자가 되기 위해서는 소자의 크기를 submicron 영역까지 줄여야 한다. 소자의 크기가 submicron까지 줄어도 end domain이 존재하는데, 이것은 자화반전을 incoherent하게 일어나게 함으로써 자기저항비를 감소시키고, 또한 자화반전을 불규칙하게 함으로써 자화반전이 일어나는 자기장의 크기가 일정하게 되지 않기 때문에 소자의 신뢰성에 큰 문제를 야기시킨다 [1]. (중략)

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.11a
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• pp.108-108
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• 2002

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• 전기의세계
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• v.30 no.10
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.