• Journal of Korean Society for Quality Management
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• v.20 no.2
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• pp.118-128
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• 1992

The determination of appropriate buffer capacity is an important issue in the design of the advanced manufacturing systems and closely related to the system efficiency and flexibility. Work-in-process is usually not desirable. However, in reality, maintaining some capacity of buffer storage is inevitable in compensation for the machine blocking and break down. The objective of this paper is to present analytical methods and tools for the buffer capacity planning in the Flexible Manufacturing System Environments. The effects when machine blocking is critical factor are also discussed.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.4
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• pp.398-405
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• 1997

This article presents a new model which is called Periodic Square-Wave(PSW) to describe the material flow of the periodic processes involving intermediate buffer. The material flows incoming into and outgoing from the intermediate buffer are assumed to be periodic square shaped. PSW model gives the same result as that of Economic Production Quantity(EPQ) model for determining optimal lot size of single stage batch storage system. However, for batch storage serial train system, PSW model gives a different optimal solution of about 6 % reduced total cost. PSW model provides the more accurate information on inventory and production system than the classical approach by maintaining simplicity and increasing computational burden.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3175-3184
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• 1997

To support large storage capacity and real-time characteristics of continuous media storage systems, we need to improve the performance of disk I/O subsystems. To improve the performance, we exploited buffer sharing scheme that reduces the number of disk I/Os. We utilized the advance knowledge of continuous media streams that is used to anticipate data demands, and so Promoting the sharing of blocks in buffers. In this paper, we proposed a buffer replacement algorithm that enables subsequent users requesting the same data to share buffer efficiently. The proposed algorithm manages buffers by utilizing reference interval information of blocks. In order to verify validity of the proposed algorithm, we accomplished simulation experiments and showed the results of performance improvements compared to traditional buffer replacement algorithms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.394-399
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• 1987

It is necessary for the speech samples to be stored in memory buffer before speech analyzers without a real time processor process them. In this paper, we propose an algorithm that uses the buffer efficiently, when the analog speech signal is converted to the digital samples by the analog to digital converter. In order to implement this method in real time, the buffer is divided into the starting buffer and the remaining buffer. Until a voiced speech is found, the converted samples are sequentially stored in the starting buffer, and then the buffer is shifted. When a voiced speech is found, the next samples are sequentally recorded in the remaining buffer.

• Applied Microscopy
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• v.19 no.2
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• pp.74-84
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• 1989

Buffer soluble storage proteins of ginseng seed have been localized by electron microscopy using post-embedding immunocytochemical gold labelling technique. Major components of the storage proteins were revealed to be storage protein-1($SP_{1}$, MW 160,000) and storage protein-2($SP_{2}$, MW 70,000). Both of the storage proteins are glycoproteins. Anti-$SP_{1}$ and anti-$SP_{2}$ from rabbit, against $SP_1$ and $SP_2$, respectively, reacted on sections of ginseng endosperm tissue embedded in Spurr's epoxy resin. The rabbit antibodies were visualized indirectly by reaction with protein A labelled with colloidal gold. Both storage proteins were found to be accumulated together in the same protein bodies, but their relative contents are not equal.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.7-12
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• 2016

DRAM is commonly used as a smartphone memory medium, but extending its capacity is challenging due to DRAM's large battery consumption and density limit. Meanwhile, smartphone applications such as social network services need increasingly large memory, resulting in long latency due to additional storage accesses. To alleviate this situation, we adopt emerging nonvolatile memory (NVRAM) as smartphone's buffer cache and propose an efficient management scheme. The proposed scheme stores all dirty data in NVRAM, thereby reducing the number of storage accesses. Moreover, it separately exploits read and write histories of data accesses, leading to more efficient management of volatile and nonvolatile buffer caches, respectively. Trace-driven simulations show that the proposed scheme improves I/O performances significantly.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.71-76
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• 2022

Buffer cache bridges the performance gap between memory and storage, but its effectiveness is limited due to periodic flush, performed to prevent data loss in smartphones. This paper shows that selective flushing technique with small persistent memory can reduce the flushing overhead of smartphone buffer cache significantly. This is due to our I/O analysis of smartphone applications in that a certain hot data account for most of file writes, while a large proportion of file data incurs single-writes. The proposed selective flushing policy performs flushing to persistent memory for frequently updated data, and storage flushing is performed only for single-write data. This eliminates storage write traffic and also improves the space efficiency of persistent memory. Simulations with popular smartphone application I/O traces show that the proposed policy reduces write traffic to storage by 24.8% on average and up to 37.8%.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• Journal of KIISE
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• v.42 no.8
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• pp.947-953
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• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.